The mechanism
DDR memory modules connect to a CPU’s memory channels and hold the working state of programs while powered. They provide substantially more capacity than small processor caches and are commonly socketed for service or expansion. DDR5 divides a module’s data interface into independent subchannels and introduces reliability features within the DRAM. On-die error correction is not the same as end-to-end protection of the complete memory link. This atlas includes DDR5 as the conventional server branch: the Grace CPU in the GB200 reference system uses LPDDR5X instead. A DDR DIMM supplies the CPU memory path in that conventional server branch; its role and interface differ from a GPU’s nearby HBM. Bandwidth depends on channel count, transfer rate, ranks, and the supported population of the motherboard.
- The CPU memory controller selects a channel and issues read or write commands to installed modules.
- DRAM devices activate and access the relevant rows, transferring values across the module’s data subchannels.
- Host software uses those values for its working set while refresh and error-management mechanisms preserve reliable operation.
Science and assumptions
Clock cycles and transfer rate are different units
CAS timing in nanoseconds is 2000 times the CAS latency count divided by the numerical DDR transfer rate in megatransfers per second.
Insert the rate number in MT/s, not transfers/s. This is CAS timing rather than complete CPU memory-access latency.
Symbols and units
- t_CAS
- CAS column-read timing interval
ns
- CL
- CAS latency count
memory clock cycles
- r_MT/s
- Numerical effective DDR transfer rate expressed in MT/s
MT/s numerical value
- 2000
- Conversion factor for two transfers per clock and MT/s to ns
conversion factor
CL is CAS latency measured in memory clock cycles. Double-data-rate signaling performs two transfers per clock, so a transfer rate of r million transfers per second corresponds to half that clock frequency. The formula converts a timing count into nanoseconds, showing why a larger CL number at a faster transfer rate can still represent similar absolute latency.
Assumptions CAS timing conversion for DDR with two transfers per clock. It covers the column-read timing interval, not total CPU load latency, row activation, precharge, queues, refresh, or burst completion. Use the selected device’s supported CL and rate together.
Engineering example
For CL=40 at 6400 MT/s, the first-order CAS estimate is 12.5 ns; controller scheduling adds delay.
Distinctions and tradeoffs
DDR5 on-die ECC protects internal DRAM operations; it is not a substitute for all end-to-end server memory error protection. Grace also uses LPDDR5X rather than these socketed DDR DIMMs.
Socketed memory offers capacity and service flexibility, but wide board routes consume energy and constrain speed. Adding modules can change the supported operating rate and access behavior.
Datasets, preprocessing buffers, retrieval indexes, and service state often live in host memory. Adequate capacity prevents expensive movement to slower storage.
Specifications and interfaces
- DDR5 data organization
- Two 32-bit subchannels per DIMM
Data bits only; server ECC modules carry additional check bits.
- Example transfer rate
- 4,800 MT/s
DDR5 example, not a universal current maximum.
- Example payload peak
- 38.4 GB/s per 64-bit module
Calculated as 4,800 million transfers/s × 8 bytes; before workload effects.
Interfaces
- CPU memory commands Input
- Addressed reads, writes, and maintenance
- Host data Output
- Application and operating-system memory values
- Refresh and power Input
- Retention maintenance and electrical supply
Check your understanding
At 4,800 MT/s and 64 data bits, what is the theoretical payload rate before workload effects?
- 38.4 GB/s.
- 4,800 GB/s.
- 38.4 TB/s.
Answer and reasoning
38.4 GB/s.
Each transfer carries 8 data bytes. Multiplying 4.8 billion transfers per second by 8 bytes gives 38.4 billion bytes per second.
Evidence and scope
The formula uses the stated transfer-rate convention.
Place read-only weights and mutable KV across specified tiers and inspect transfer paths; no HBF shipping-system benchmark or universal memory semantics are implied.