The mechanism
The baseboard is where separate components become a coordinated machine. Its traces and connectors join processors, memory, storage, network adapters, management, and power circuits. A compute tray adds mechanical support, cooling connections, and interfaces that let the assembly slide into a rack. Topology matters: which GPU reaches which NIC, which devices share a PCIe path, and where CPU memory sits can all affect performance. Board signal routes, power distribution and cooling connections impose different constraints on the same operating assembly. This view is a logical reconstruction based on published block diagrams, not a manufacturing drawing. The serviceable tray is the bridge between package-scale engineering and rack-scale operations.
- The board physically mounts the computing, memory, I/O, control, and power components and connects their electrical interfaces.
- The tray integrates that board with structural support, cooling paths, and rack-facing connectors.
- Power, data, management, and heat flow through separate but coordinated paths while the node executes its workload.
Science and assumptions
Impedance discontinuities reflect fast signals
The voltage reflection coefficient is load impedance minus characteristic impedance divided by their sum.
Symbols and units
- Γ
- Voltage reflection coefficient
dimensionless (potentially complex)
- Z_load
- Termination impedance
Ω
- Z₀
- Transmission-line characteristic impedance
Ω
Z0 is the transmission-line characteristic impedance and Zload is the termination impedance. Γ is the voltage reflection coefficient: a matched resistive load gives zero reflection, an open approaches +1, and a short approaches −1. Traces, vias, connectors, and package transitions must be designed together because reflected energy can distort the eye opening used to distinguish high-speed bits.
Assumptions An ideal linear transmission line at a single termination, with real resistances for the simple limiting examples. Loss, frequency-dependent impedance, differential coupling, equalization, and multiple discontinuities require fuller channel analysis.
Engineering example
Synthetic resistive termination: a 50 Ω line meeting a 75 Ω load has reflection coefficient Γ = (75 − 50)/(75 + 50) = 0.2. A 1 V incident wave therefore has a 0.2 V reflected wave at that boundary. A matched 50 Ω load gives Γ = 0.
Distinctions and tradeoffs
A compute tray is not just a row of GPUs. CPU affinity, network paths, power delivery, cooling, and service connections all affect its practical behavior.
Dense integration shortens paths and saves space but complicates routing, cooling, and repair. A good board design balances peak performance with manufacturability and serviceability.
The GPU’s performance is useful only when data, power, and heat can move through the surrounding node. The tray makes those dependencies physically explicit.
Specifications and interfaces
- DGX GB200 tray
- 2 Grace CPUs + 4 Blackwell GPUs
Published compute-tray configuration.
- Mechanical height
- 1 RU per compute tray
DGX GB200 reference; 1 RU is 44.45 mm nominal rack-unit spacing.
- Tray count in NVL72
- 18 compute trays
Four GPUs per tray gives 72 GPUs in the rack.
Interfaces
- Power and coolant Input
- Rack distribution to board regulators and coldplates
- External network Output
- Scale-out and management connections
- GPU fabric Output
- NVLink connections toward rack switching
Check your understanding
Why inspect a compute tray’s topology before distributing a workload?
- Every component has an identical path to every other component.
- Topology only changes the tray’s appearance.
- Shared links and device proximity can change communication costs.
Answer and reasoning
Shared links and device proximity can change communication costs.
Topology reveals which paths are local, shared, or remote. Work placement can avoid unnecessary traffic and contention.
Evidence and scope
This is the lesson’s single-termination linear transmission-line model. Values are synthetic; differential geometry, frequency response, loss, multiple reflections and receiver behavior need a complete channel model.
No current calculator directly models this lesson’s main mechanism. Use the library for related bounds while retaining their stated omissions.