GPU logic dies

The mechanism

A logic die is a piece cut from a processed silicon wafer. Its surface carries layers of transistors and metal interconnect that implement arithmetic, memories, control, and interfaces. Datacenter Blackwell combines two large logic dies into one GPU, crossing the boundary with a dedicated high-bandwidth interface. This permits more circuitry than one exposure-sized die while preserving a single accelerator programming view. The package must connect those dies to each other, to memory stacks, and to power and cooling structures. Functional regions explain the die’s roles, but schematic proportions are not a verified proprietary floorplan. The die-to-die connection carries many parallel transfers, making package communication part of the architecture rather than merely a protective enclosure.

Wafer fabrication builds transistors and interconnect layers implementing logic, memory, control, and interfaces.
After testing and singulation, suitable dies are assembled with memory and dense interconnect structures into an accelerator package.
The packaged GPU receives instructions, data, power, and cooling, then repeatedly reuses its circuits for many software operations.

Science and assumptions

Switching activity becomes heat

P_{\mathrm{dynamic}}\approx\alpha C_{\mathrm{switched}}V^2f

Dynamic power is approximately activity times switched capacitance times voltage squared times clock frequency.

Symbols and units

P_dynamic: Dynamic switching power
W
α: Effective charging activity per clock period
events/cycle
C_switched: Effective switched capacitance
F
V: Supply voltage
V
f: Clock frequency
cycles/s

α is the average charging activity per clock, Cswitched is effective switched capacitance, V is supply voltage, and f is clock frequency. Raising voltage has a quadratic effect in this model, while raising frequency has a linear effect. Consequently, adding transistors or increasing clocks does not provide free computation; energy-efficient architecture also reduces moved capacitance and unnecessary switching.

Assumptions First-order CMOS capacitive switching model. Leakage, short-circuit current, clock networks, memory, I/O, and conversion losses contribute additional power; voltage and frequency are not independent across valid operating points. No Blackwell rail value is inferred.

Engineering example

At fixed capacitance and frequency, a 10% voltage increase raises the first-order dynamic term by about 21%, before leakage and regulator losses.

Distinctions and tradeoffs

A Blackwell GPU’s 208 billion transistor count describes the combined two-die GPU, not 208 billion transistors in each die or each Superchip component.

Splitting a large processor can extend integration beyond a single die limit, but adds package and communication demands. Yield, testing, routing, and heat must be solved together.

The die converts numerical instructions into physical switching activity. Its architecture determines how much useful matrix computation can be sustained for a given supply of data and power.

Specifications and interfaces

Integration: 2 large logic dies per GPU
Datacenter Blackwell design described by NVIDIA.
Transistor count: 208 billion per GPU
Combined Blackwell GPU count, not a count for each die.
Die-to-die link: 10 TB/s
NVIDIA-reported interface bandwidth; do not relabel it NVLink.

Interfaces

Power and clock Input: Supply rails, timing, and control
Memory and peer data Input: HBM and adjacent-die transactions
Computed results Output: Memory stores and accelerator communication

Check your understanding

Why use two large logic dies within one GPU?

To give each model layer a permanent physical home.
To avoid needing any package wiring.
To integrate more circuitry than one exposure-sized logic die can provide.

Answer and reasoning

To integrate more circuitry than one exposure-sized logic die can provide.

Multiple dies extend integration beyond a single die boundary, but require fast interconnect, advanced packaging, testing, and thermal management.

Historical context

2024 · Blackwell extends acceleration from multiple dies to rack-scale systems

Announced on March 18, 2024, Blackwell joined two large logic dies within one GPU and paired new numerical formats with stronger GPU interconnect. Grace Blackwell systems brought CPU, GPU memory, scale-up networking, power, and cooling into a more tightly coordinated architecture; no specific proprietary model’s deployment is implied.

NVIDIA: Blackwell platform announcement

Evidence and scope

The model does not disclose or infer a specific GPU rail or Astra design.

Follow a modeled batched decode critical path and energy budget; prefill, expert routing and scheduling differences are comparison context rather than separately simulated algorithms.