{"id":"gpu-die","level":"package","name":"GPU logic dies","shortName":"GPU dies","role":"Integrate transistor circuits into the compute, storage, and communication structures of one accelerator.","description":"A logic die is a piece cut from a processed silicon wafer. Its surface carries layers of transistors and metal interconnect that implement arithmetic, memories, control, and interfaces. Datacenter Blackwell combines two large logic dies into one GPU, crossing the boundary with a dedicated high-bandwidth interface. This permits more circuitry than one exposure-sized die while preserving a single accelerator programming view. The package must connect those dies to each other, to memory stacks, and to power and cooling structures. Functional regions explain the die’s roles, but schematic proportions are not a verified proprietary floorplan. The die-to-die connection carries many parallel transfers, making package communication part of the architecture rather than merely a protective enclosure.","specs":[{"label":"Integration","value":"2 large logic dies per GPU","context":"Datacenter Blackwell design described by NVIDIA."},{"label":"Transistor count","value":"208 billion per GPU","context":"Combined Blackwell GPU count, not a count for each die."},{"label":"Die-to-die link","value":"10 TB/s","context":"NVIDIA-reported interface bandwidth; do not relabel it NVLink."}],"interfaces":[{"name":"Power and clock","direction":"in","signal":"Supply rails, timing, and control"},{"name":"Memory and peer data","direction":"in","signal":"HBM and adjacent-die transactions"},{"name":"Computed results","direction":"out","signal":"Memory stores and accelerator communication"}],"tradeoff":"Splitting a large processor can extend integration beyond a single die limit, but adds package and communication demands. Yield, testing, routing, and heat must be solved together.","whyAI":"The die converts numerical instructions into physical switching activity. Its architecture determines how much useful matrix computation can be sustained for a given supply of data and power.","related":["streaming-multiprocessor","on-chip-network","hbm-stack","interposer","thermal-interface","grace-blackwell-superchip"],"sources":[{"title":"NVIDIA Blackwell platform announcement","url":"https://nvidianews.nvidia.com/news/nvidia-blackwell-platform-arrives-to-power-a-new-era-of-computing"},{"title":"Texas Instruments: CMOS dynamic power","url":"https://www.ti.com/lit/pdf/sprac07"}],"scale":"Centimeter-scale logic dies; exact die dimensions not asserted","kind":"dual-die-functional-cutaway","mechanism":["Wafer fabrication builds transistors and interconnect layers implementing logic, memory, control, and interfaces.","After testing and singulation, suitable dies are assembled with memory and dense interconnect structures into an accelerator package.","The packaged GPU receives instructions, data, power, and cooling, then repeatedly reuses its circuits for many software operations."],"misconception":"A Blackwell GPU’s 208 billion transistor count describes the combined two-die GPU, not 208 billion transistors in each die or each Superchip component.","check":{"question":"Why use two large logic dies within one GPU?","options":["To give each model layer a permanent physical home.","To avoid needing any package wiring.","To integrate more circuitry than one exposure-sized logic die can provide."],"answer":2,"explanation":"Multiple dies extend integration beyond a single die boundary, but require fast interconnect, advanced packaging, testing, and thermal management."},"branch":"Advanced packaging","subbranch":"Logic integration","science":[{"title":"Switching activity becomes heat","equation":"Pdynamic ≈ α × Cswitched × V² × f","explanation":"α is the average charging activity per clock, Cswitched is effective switched capacitance, V is supply voltage, and f is clock frequency. Raising voltage has a quadratic effect in this model, while raising frequency has a linear effect. Consequently, adding transistors or increasing clocks does not provide free computation; energy-efficient architecture also reduces moved capacitance and unnecessary switching.","assumptions":"First-order CMOS capacitive switching model. Leakage, short-circuit current, clock networks, memory, I/O, and conversion losses contribute additional power; voltage and frequency are not independent across valid operating points. No Blackwell rail value is inferred."}],"history":[{"year":2024,"title":"Blackwell extends acceleration from multiple dies to rack-scale systems","significance":"Announced on March 18, 2024, Blackwell joined two large logic dies within one GPU and paired new numerical formats with stronger GPU interconnect. Grace Blackwell systems brought CPU, GPU memory, scale-up networking, power, and cooling into a more tightly coordinated architecture; no specific proprietary model’s deployment is implied.","source":{"title":"NVIDIA: Blackwell platform announcement","url":"https://nvidianews.nvidia.com/news/nvidia-blackwell-platform-arrives-to-power-a-new-era-of-computing"}}],"learningObjective":"Connect switching activity to package-level heat.","engineeringExample":"At fixed capacitance and frequency, a 10% voltage increase raises the first-order dynamic term by about 21%, before leakage and regulator losses.","evidenceNotes":"The model does not disclose or infer a specific GPU rail or Astra design.","visualFamily":"package-route","prerequisites":["streaming-multiprocessor","on-chip-network"],"labId":"token-system-path","scope":"Follow a modeled batched decode critical path and energy budget; prefill, expert routing and scheduling differences are comparison context rather than separately simulated algorithms.","investigationId":"execution","labScope":"Follow a modeled batched decode critical path and energy budget; prefill, expert routing and scheduling differences are comparison context rather than separately simulated algorithms."}