{"id":"compute-baseboard","level":"server","name":"Compute baseboard and tray","shortName":"Compute tray","role":"Integrates processors, memory, adapters, power, cooling, and service interfaces into an operational node.","description":"The baseboard is where separate components become a coordinated machine. Its traces and connectors join processors, memory, storage, network adapters, management, and power circuits. A compute tray adds mechanical support, cooling connections, and interfaces that let the assembly slide into a rack. Topology matters: which GPU reaches which NIC, which devices share a PCIe path, and where CPU memory sits can all affect performance. Board signal routes, power distribution and cooling connections impose different constraints on the same operating assembly. This view is a logical reconstruction based on published block diagrams, not a manufacturing drawing. The serviceable tray is the bridge between package-scale engineering and rack-scale operations.","specs":[{"label":"DGX GB200 tray","value":"2 Grace CPUs + 4 Blackwell GPUs","context":"Published compute-tray configuration."},{"label":"Mechanical height","value":"1 RU per compute tray","context":"DGX GB200 reference; 1 RU is 44.45 mm nominal rack-unit spacing."},{"label":"Tray count in NVL72","value":"18 compute trays","context":"Four GPUs per tray gives 72 GPUs in the rack."}],"interfaces":[{"name":"Power and coolant","direction":"in","signal":"Rack distribution to board regulators and coldplates"},{"name":"External network","direction":"out","signal":"Scale-out and management connections"},{"name":"GPU fabric","direction":"out","signal":"NVLink connections toward rack switching"}],"tradeoff":"Dense integration shortens paths and saves space but complicates routing, cooling, and repair. A good board design balances peak performance with manufacturability and serviceability.","whyAI":"The GPU’s performance is useful only when data, power, and heat can move through the surrounding node. The tray makes those dependencies physically explicit.","related":["host-cpu","grace-blackwell-superchip","network-adapter","nvme-storage","voltage-regulator","coldplate","management-controller","package-substrate","compute-tray"],"sources":[{"title":"NVIDIA DGX GB200 SuperPOD reference components","url":"https://docs.nvidia.com/dgx-superpod/reference-architecture-scalable-infrastructure-gb200/latest/dgx-superpod-components.html"},{"title":"NVIDIA GB200 NVL multi-node tuning: system topology","url":"https://docs.nvidia.com/multi-node-nvlink-systems/multi-node-tuning-guide/system.html"},{"title":"Texas Instruments: High-Speed Layout Guidelines","url":"https://www.ti.com/lit/pdf/SCAA082A"}],"scale":"Roughly rack-width board/tray assembly; published 1 RU height","kind":"exploded-compute-tray","mechanism":["The board physically mounts the computing, memory, I/O, control, and power components and connects their electrical interfaces.","The tray integrates that board with structural support, cooling paths, and rack-facing connectors.","Power, data, management, and heat flow through separate but coordinated paths while the node executes its workload."],"misconception":"A compute tray is not just a row of GPUs. CPU affinity, network paths, power delivery, cooling, and service connections all affect its practical behavior.","check":{"question":"Why inspect a compute tray’s topology before distributing a workload?","options":["Every component has an identical path to every other component.","Topology only changes the tray’s appearance.","Shared links and device proximity can change communication costs."],"answer":2,"explanation":"Topology reveals which paths are local, shared, or remote. Work placement can avoid unnecessary traffic and contention."},"branch":"System integration","subbranch":"Boards and modules","science":[{"title":"Impedance discontinuities reflect fast signals","equation":"Γ = (Zload − Z0) / (Zload + Z0)","explanation":"Z0 is the transmission-line characteristic impedance and Zload is the termination impedance. Γ is the voltage reflection coefficient: a matched resistive load gives zero reflection, an open approaches +1, and a short approaches −1. Traces, vias, connectors, and package transitions must be designed together because reflected energy can distort the eye opening used to distinguish high-speed bits.","assumptions":"An ideal linear transmission line at a single termination, with real resistances for the simple limiting examples. Loss, frequency-dependent impedance, differential coupling, equalization, and multiple discontinuities require fuller channel analysis."}],"history":[],"prerequisites":["gpu-die","package-substrate","pcie-interface"],"learningObjective":"Use an impedance discontinuity to explain why a logically connected board trace can distort a signal.","engineeringExample":"Synthetic resistive termination: a 50 Ω line meeting a 75 Ω load has reflection coefficient Γ = (75 − 50)/(75 + 50) = 0.2. A 1 V incident wave therefore has a 0.2 V reflected wave at that boundary. A matched 50 Ω load gives Γ = 0.","evidenceNotes":"This is the lesson’s single-termination linear transmission-line model. Values are synthetic; differential geometry, frequency response, loss, multiple reflections and receiver behavior need a complete channel model.","labId":"library","scope":"No current calculator directly models this lesson’s main mechanism. Use the library for related bounds while retaining their stated omissions.","investigationId":"execution","labScope":"No current calculator directly models this lesson’s main mechanism. Use the library for related bounds while retaining their stated omissions."}