The mechanism
A DRAM die is mostly an organized landscape of memory cells. In the common one-transistor, one-capacitor cell, stored charge represents a bit and the transistor controls access to it. Word lines select rows; bit lines carry the small electrical changes that sense amplifiers detect and restore. The charge leaks, so refresh is part of normal operation. Banks provide opportunities for overlapping work, but timing constraints mean that an arbitrary stream of addresses does not behave like one continuous pipe. A memory bank organizes rows of cells; the stored bits collectively encode the weight and activation arrays that software reads and writes.
- A selected word line enables access transistors, coupling the chosen memory cells to their bit lines.
- Sense amplifiers detect and restore small charge-dependent signals so reads produce reliable digital values.
- Refresh revisits stored rows before leakage destroys their contents, while banks schedule application accesses around maintenance.
Science and assumptions
A stored bit begins as a tiny voltage perturbation
Initial bit-line voltage change is the cell share of total capacitance times the initial cell-to-precharge voltage difference.
Symbols and units
- ΔV_bitline
- Initial bit-line voltage change
V
- C_cell
- Selected cell capacitance
F
- C_bitline
- Precharged bit-line capacitance
F
- V_cell
- Cell voltage before charge sharing
V
- V_precharge
- Bit-line precharge voltage
V
When the access transistor connects a selected cell to a precharged bit line, their capacitances share charge. Because the bit line can be much larger than the cell capacitance, the initial voltage change is small. A sense amplifier must detect its sign and restore a full logic level, connecting the microscopic capacitor directly to the digital bit used by software.
Assumptions Ideal charge sharing before amplification, with fixed capacitances and no leakage, access resistance, coupling noise, or transistor threshold effects. Actual DRAM sensing and retention require a full circuit model.
Engineering example
A cell charge is shared with a bitline capacitance before the sense amplifier resolves and restores the value; parasitics reduce the ideal swing.
Distinctions and tradeoffs
DRAM retains information only while powered and refreshed. The trained model survives a power loss because a separate nonvolatile copy exists in storage.
DRAM provides more bits per area than SRAM, but access and refresh require additional operations. Higher density must preserve enough electrical margin for reliable sensing.
Billions of model parameters are ultimately stored as physical bit patterns. DRAM supplies the capacity that small on-chip SRAM structures cannot economically provide.
Specifications and interfaces
- Cell model
- 1 transistor + 1 capacitor
Common DRAM cell; schematic, not a manufacturer-specific process cross-section.
- State retention
- Volatile; periodic refresh
Stored charge requires maintenance while powered.
- Example per-layer density
- 24 Gb = 3 GB
Inferred average for 24 GB/8-layer and 36 GB/12-layer HBM3E examples.
Interfaces
- Row/column selection Input
- Decoded memory commands
- Sensed data Output
- Restored digital values from selected cells
- Refresh control Input
- Operations that restore stored charge
Check your understanding
Why does conventional DRAM need refresh?
- Stored capacitor charge gradually leaks away.
- Every memory cell is an optical fiber.
- Refresh downloads a new model from the network.
Answer and reasoning
Stored capacitor charge gradually leaks away.
Charge-based storage is compact but not indefinitely stable. Periodic restoration keeps the bit values intact while power is available.
Historical context
1968 · Dennard’s DRAM cell patent is granted
Robert Dennard’s field-effect memory patent, filed in 1967 after his 1966 work at IBM, was granted on June 4, 1968. A compact access device and charge-storage element established the basis for dense dynamic memory, with periodic restoration as part of normal operation.
Evidence and scope
The expression is a simplified charge-sharing model.
Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.