{"id":"dram-die","level":"package","name":"DRAM die and memory banks","shortName":"DRAM die","role":"Stores dense arrays of charge-based bits and organizes them into banks for read, write, and refresh.","description":"A DRAM die is mostly an organized landscape of memory cells. In the common one-transistor, one-capacitor cell, stored charge represents a bit and the transistor controls access to it. Word lines select rows; bit lines carry the small electrical changes that sense amplifiers detect and restore. The charge leaks, so refresh is part of normal operation. Banks provide opportunities for overlapping work, but timing constraints mean that an arbitrary stream of addresses does not behave like one continuous pipe. A memory bank organizes rows of cells; the stored bits collectively encode the weight and activation arrays that software reads and writes.","specs":[{"label":"Cell model","value":"1 transistor + 1 capacitor","context":"Common DRAM cell; schematic, not a manufacturer-specific process cross-section."},{"label":"State retention","value":"Volatile; periodic refresh","context":"Stored charge requires maintenance while powered."},{"label":"Example per-layer density","value":"24 Gb = 3 GB","context":"Inferred average for 24 GB/8-layer and 36 GB/12-layer HBM3E examples."}],"interfaces":[{"name":"Row/column selection","direction":"in","signal":"Decoded memory commands"},{"name":"Sensed data","direction":"out","signal":"Restored digital values from selected cells"},{"name":"Refresh control","direction":"in","signal":"Operations that restore stored charge"}],"tradeoff":"DRAM provides more bits per area than SRAM, but access and refresh require additional operations. Higher density must preserve enough electrical margin for reliable sensing.","whyAI":"Billions of model parameters are ultimately stored as physical bit patterns. DRAM supplies the capacity that small on-chip SRAM structures cannot economically provide.","related":["hbm-stack","through-silicon-via","ddr-memory","lpddr-memory"],"sources":[{"title":"Micron: How DRAM changed the world","url":"https://www.micron.com/about/blog/memory/dram/how-dram-changed-the-world"},{"title":"Micron educator hub: Introduction to memory","url":"https://www.micron.com/content/dam/micron/educatorhub/intro-to-memory/micron-intro-to-memory-presentation.pdf"},{"title":"Micron HBM3E","url":"https://www.micron.com/products/memory/hbm/hbm3e"},{"title":"MIT Computation Structures: DRAM charge sharing","url":"https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/f342551f652653e3ee0d0c56a926efeb_9eWKuWyXYKY.pdf"},{"title":"Robert Dennard: US3387286A, Field-effect transistor memory","url":"https://patents.google.com/patent/US3387286A/en"}],"scale":"Nanometer-scale device features assembled into millimeter-scale banks and dies","kind":"dram-bank-to-cell","mechanism":["A selected word line enables access transistors, coupling the chosen memory cells to their bit lines.","Sense amplifiers detect and restore small charge-dependent signals so reads produce reliable digital values.","Refresh revisits stored rows before leakage destroys their contents, while banks schedule application accesses around maintenance."],"misconception":"DRAM retains information only while powered and refreshed. The trained model survives a power loss because a separate nonvolatile copy exists in storage.","check":{"question":"Why does conventional DRAM need refresh?","options":["Stored capacitor charge gradually leaks away.","Every memory cell is an optical fiber.","Refresh downloads a new model from the network."],"answer":0,"explanation":"Charge-based storage is compact but not indefinitely stable. Periodic restoration keeps the bit values intact while power is available."},"branch":"Memory hierarchy","subbranch":"Stacked DRAM","science":[{"title":"A stored bit begins as a tiny voltage perturbation","equation":"ΔVbitline = [Ccell / (Ccell + Cbitline)] × (Vcell − Vprecharge)","explanation":"When the access transistor connects a selected cell to a precharged bit line, their capacitances share charge. Because the bit line can be much larger than the cell capacitance, the initial voltage change is small. A sense amplifier must detect its sign and restore a full logic level, connecting the microscopic capacitor directly to the digital bit used by software.","assumptions":"Ideal charge sharing before amplification, with fixed capacitances and no leakage, access resistance, coupling noise, or transistor threshold effects. Actual DRAM sensing and retention require a full circuit model."}],"history":[{"year":1968,"title":"Dennard’s DRAM cell patent is granted","significance":"Robert Dennard’s field-effect memory patent, filed in 1967 after his 1966 work at IBM, was granted on June 4, 1968. A compact access device and charge-storage element established the basis for dense dynamic memory, with periodic restoration as part of normal operation.","source":{"title":"Robert Dennard: US3387286A, Field-effect transistor memory","url":"https://patents.google.com/patent/US3387286A/en"}}],"learningObjective":"Follow a bitline disturbance through sensing and restoration.","engineeringExample":"A cell charge is shared with a bitline capacitance before the sense amplifier resolves and restores the value; parasitics reduce the ideal swing.","evidenceNotes":"The expression is a simplified charge-sharing model.","visualFamily":"hbm-detail","prerequisites":["mosfet","dielectric"],"labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}