{"id":"ddr-memory","level":"server","name":"DDR5 server memory","shortName":"DDR5 DIMM","role":"Provides expandable main memory for conventional host CPUs and their software working sets.","description":"DDR memory modules connect to a CPU’s memory channels and hold the working state of programs while powered. They provide substantially more capacity than small processor caches and are commonly socketed for service or expansion. DDR5 divides a module’s data interface into independent subchannels and introduces reliability features within the DRAM. On-die error correction is not the same as end-to-end protection of the complete memory link. This atlas includes DDR5 as the conventional server branch: the Grace CPU in the GB200 reference system uses LPDDR5X instead. A DDR DIMM supplies the CPU memory path in that conventional server branch; its role and interface differ from a GPU’s nearby HBM. Bandwidth depends on channel count, transfer rate, ranks, and the supported population of the motherboard.","specs":[{"label":"DDR5 data organization","value":"Two 32-bit subchannels per DIMM","context":"Data bits only; server ECC modules carry additional check bits."},{"label":"Example transfer rate","value":"4,800 MT/s","context":"DDR5 example, not a universal current maximum."},{"label":"Example payload peak","value":"38.4 GB/s per 64-bit module","context":"Calculated as 4,800 million transfers/s × 8 bytes; before workload effects."}],"interfaces":[{"name":"CPU memory commands","direction":"in","signal":"Addressed reads, writes, and maintenance"},{"name":"Host data","direction":"out","signal":"Application and operating-system memory values"},{"name":"Refresh and power","direction":"in","signal":"Retention maintenance and electrical supply"}],"tradeoff":"Socketed memory offers capacity and service flexibility, but wide board routes consume energy and constrain speed. Adding modules can change the supported operating rate and access behavior.","whyAI":"Datasets, preprocessing buffers, retrieval indexes, and service state often live in host memory. Adequate capacity prevents expensive movement to slower storage.","related":["host-cpu","dram-die","compute-baseboard","lpddr-memory"],"sources":[{"title":"Micron DDR5 DRAM","url":"https://www.micron.com/products/memory/dram-components/ddr5-sdram"},{"title":"Micron DDR5 SDRAM: New Features","url":"https://assets.micron.com/adobe/assets/urn%3Aaaid%3Aaem%3A5ea148c8-e3fe-489e-8489-99b1b9cdcd3c/renditions/original/as/ddr5-new-features-white-paper.pdf"}],"scale":"About 10-centimeter module class; multiple packaged DRAM devices","kind":"dimm-to-memory-bank","mechanism":["The CPU memory controller selects a channel and issues read or write commands to installed modules.","DRAM devices activate and access the relevant rows, transferring values across the module’s data subchannels.","Host software uses those values for its working set while refresh and error-management mechanisms preserve reliable operation."],"misconception":"DDR5 on-die ECC protects internal DRAM operations; it is not a substitute for all end-to-end server memory error protection. Grace also uses LPDDR5X rather than these socketed DDR DIMMs.","check":{"question":"At 4,800 MT/s and 64 data bits, what is the theoretical payload rate before workload effects?","options":["38.4 GB/s.","4,800 GB/s.","38.4 TB/s."],"answer":0,"explanation":"Each transfer carries 8 data bytes. Multiplying 4.8 billion transfers per second by 8 bytes gives 38.4 billion bytes per second."},"branch":"Host platform","subbranch":"CPU main memory","science":[{"title":"Clock cycles and transfer rate are different units","equation":"tCAS(ns) = 2,000 × CL / rMT/s","explanation":"CL is CAS latency measured in memory clock cycles. Double-data-rate signaling performs two transfers per clock, so a transfer rate of r million transfers per second corresponds to half that clock frequency. The formula converts a timing count into nanoseconds, showing why a larger CL number at a faster transfer rate can still represent similar absolute latency.","assumptions":"CAS timing conversion for DDR with two transfers per clock. It covers the column-read timing interval, not total CPU load latency, row activation, precharge, queues, refresh, or burst completion. Use the selected device’s supported CL and rate together."}],"history":[],"learningObjective":"Convert a CAS latency and transfer rate into a time estimate.","engineeringExample":"For CL=40 at 6400 MT/s, the first-order CAS estimate is 12.5 ns; controller scheduling adds delay.","evidenceNotes":"The formula uses the stated transfer-rate convention.","visualFamily":"memory-route","prerequisites":["dram-die","host-cpu"],"labId":"inference-placement","scope":"Place read-only weights and mutable KV across specified tiers and inspect transfer paths; no HBF shipping-system benchmark or universal memory semantics are implied.","investigationId":"execution","labScope":"Place read-only weights and mutable KV across specified tiers and inspect transfer paths; no HBF shipping-system benchmark or universal memory semantics are implied."}