Redistribution layers and fan-out packaging

The mechanism

A redistribution layer adds conductive routing over a prepared surface to move connection locations. Fan-out packaging can place dies in a larger reconstructed or molded area and build routing that extends beyond the original die edge. This provides more room for external connections or multiple components, but the reconstructed geometry brings alignment, warpage and material challenges. Chip-first and chip-last flows do not use the same operation order, so the reference sequence names its route. RDL is also a building block in several advanced integration families; seeing it in a package does not establish that every such package has an identical interposer or assembly process.

Choose and label a chip-first or chip-last reference route before animating its sequence.
Create a stable reconstruction or carrier surface with recorded die positions.
Build dielectric, openings and conductive redistribution using the route’s compatible processing steps.
Account for die shift, surface distortion and alignment while connecting original pads.
Release temporary support where required, complete joints and inspect electrical and mechanical integrity.

Science and assumptions

Registration budget

e_{\mathrm{total}}^2\approx e_{\mathrm{place}}^2+e_{\mathrm{pattern}}^2+e_{\mathrm{distortion}}^2

For independent zero-mean alignment contributions, the combined squared error is approximately the sum of their squared contributions.

Symbols and units

e_total: Combined standard-deviation-like alignment contribution
μm
e_place: Placement contribution
μm
e_pattern: Patterning contribution
μm
e_distortion: Residual distortion contribution
μm

Each e is a standard-deviation-like alignment contribution in the same length unit.

Assumptions Root-sum-square model only for independent zero-mean contributions. Systematic offsets must be corrected or budgeted explicitly.

Engineering example

Synthetic independent alignment terms of 2, 1 and 2 μm combine to 3 μm RMS. If the 2 μm placement term is systematic, averaging more measurements does not erase its physical offset.

Distinctions and tradeoffs

Fan-out does not simply mean a physically larger silicon die; added routing can occupy a different surrounding material.

Extending routing area can reduce pad-density pressure but increases reconstructed-surface alignment and thermomechanical demands.

Package-level routing can combine useful dies and interfaces when a single monolithic die or direct substrate escape is impractical.

Specifications and interfaces

Geometry: Die footprint vs reconstructed package area
Fan-out refers to routing beyond the original die boundary.
RDL function: Redistributed signal and power connections
RDL can appear in several process and package families.

Interfaces

Dies and temporary/reconstructed surface Input: Placement map and compatible exposed connection sites
Redistributed interface Output: New routing and external pad arrangement

Check your understanding

Why can die placement error matter before RDL patterning?

A molded surface automatically corrects all coordinates
Redistribution carries no current
The later routing must land on the actual die-pad positions

Answer and reasoning

The later routing must land on the actual die-pad positions

Geometric mismatch between planned routes and real pads can cause opens or shorts even if each die itself is good.

Evidence and scope

The lesson shows a generic reconstruction sequence, not a vendor’s complete fan-out recipe or qualified alignment budget.

Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.