CoWoS-R and CoWoS-L: RDL and local silicon

The mechanism

CoWoS-R and CoWoS-L are different routing arrangements within TSMC’s package family. CoWoS-R uses an RDL interposer composed of polymer and copper routing. CoWoS-L combines an RDL-based interposer with embedded local silicon interconnects where denser connections are needed. These distinctions change the geometry and material system compared with a broad silicon interposer. A useful comparison keeps the same logic and memory endpoints while exposing where each route carries dense signals and distributes power. Larger package capability alone does not establish better yield, lower cost or interchangeable production capacity; those require a complete configuration and manufacturing boundary.

Hold the compute and memory endpoint requirements fixed for the route comparison.
For CoWoS-R, identify the polymer/copper RDL interposer that connects those endpoints.
For CoWoS-L, place local silicon interconnects at dense-link locations and connect the wider RDL network.
Integrate compatible dies and substrate connections while controlling alignment and material deformation.
Compare complete routing, power, thermal, test and manufacturing requirements rather than one advertised package dimension.

Science and assumptions

Dense-routing footprint accounting

A_{\mathrm{dense}}=\sum_i A_{\mathrm{local},i},\qquad f_{\mathrm{dense}}=\frac{A_{\mathrm{dense}}}{A_{\mathrm{package}}}

Dense-routing area is the sum of its local regions. Dividing by package area gives the footprint fraction.

Symbols and units

A_dense: Total dense-routing area counted without overlap
mm²
A_local,i: Area of dense-routing region i
mm²
A_package: Package area using the same footprint convention
mm²
f_dense: Dense-routing area fraction
dimensionless
i: Included region index
integer index

Areas use the same unit and fraction is dimensionless.

Assumptions Geometric bookkeeping only; lower dense-silicon area does not directly predict cost, yield, bandwidth or capacity.

Engineering example

Synthetic diagram: four local routing pieces of 10 mm² total 40 mm² inside a 1,000 mm² package outline. The 4% area fraction describes placement only; it is not a 96% cost or yield improvement.

Distinctions and tradeoffs

CoWoS-S, CoWoS-R and CoWoS-L are not merely three names for identical geometry.

Concentrating fine routing locally can reduce the need for a broad fine-routing silicon plane while adding placement and heterogeneous-material integration tasks.

As accelerators need more logic and memory within a package, routing location and material choices become system design decisions.

Specifications and interfaces

CoWoS-R: Polymer/copper RDL interposer
A routing construction, not the same as a full silicon interposer.
CoWoS-L: RDL plus local silicon interconnects
Dense local silicon and wider-area redistribution have different roles.

Interfaces

Logic, memory and routing components Input: Compatible endpoints and route-specific fabricated structures
Integrated routing assembly Output: Dense local links plus package-wide signal/power paths

Check your understanding

Which feature distinguishes the CoWoS-L description from an RDL-only interposer?

All memory is fabricated inside the logic die
Embedded local silicon interconnects for dense links
The absence of any conductive routing

Answer and reasoning

Embedded local silicon interconnects for dense links

CoWoS-L combines local high-density silicon routing with a broader RDL-based structure.

Evidence and scope

Public route definitions are checked; variant-specific tool capacity and customer queues are unknown. Production-history dates remain separate evidence entries.

Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.