{"id":"rdl-fanout-integration","level":"package","name":"Redistribution layers and fan-out packaging","shortName":"Redistribution layers and fan-out packaging","role":"Routes die connections through added layers that can extend beyond the die footprint.","description":"A redistribution layer adds conductive routing over a prepared surface to move connection locations. Fan-out packaging can place dies in a larger reconstructed or molded area and build routing that extends beyond the original die edge. This provides more room for external connections or multiple components, but the reconstructed geometry brings alignment, warpage and material challenges. Chip-first and chip-last flows do not use the same operation order, so the reference sequence names its route. RDL is also a building block in several advanced integration families; seeing it in a package does not establish that every such package has an identical interposer or assembly process.","specs":[{"label":"Geometry","value":"Die footprint vs reconstructed package area","context":"Fan-out refers to routing beyond the original die boundary."},{"label":"RDL function","value":"Redistributed signal and power connections","context":"RDL can appear in several process and package families."}],"interfaces":[{"name":"Dies and temporary/reconstructed surface","direction":"in","signal":"Placement map and compatible exposed connection sites"},{"name":"Redistributed interface","direction":"out","signal":"New routing and external pad arrangement"}],"tradeoff":"Extending routing area can reduce pad-density pressure but increases reconstructed-surface alignment and thermomechanical demands.","whyAI":"Package-level routing can combine useful dies and interfaces when a single monolithic die or direct substrate escape is impractical.","related":["cowos-r-l-routing","flip-chip-abf-substrate","temporary-carrier-thinning"],"sources":[{"title":"SK hynix — Small Size, Big Impact","url":"https://news.skhynix.com/en/small-size-big-impact/"},{"title":"TSMC — CoWoS","url":"https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm"},{"title":"Amkor — Flip Chip Packaging","url":"https://amkor.com/technology/flip-chip/"}],"scale":"Die pads to package and board; routing pitch schematic","kind":"integration","branch":"Packaging / Materials and assembly","subbranch":"Package routing foundations","mechanism":["Choose and label a chip-first or chip-last reference route before animating its sequence.","Create a stable reconstruction or carrier surface with recorded die positions.","Build dielectric, openings and conductive redistribution using the route’s compatible processing steps.","Account for die shift, surface distortion and alignment while connecting original pads.","Release temporary support where required, complete joints and inspect electrical and mechanical integrity."],"misconception":"Fan-out does not simply mean a physically larger silicon die; added routing can occupy a different surrounding material.","check":{"question":"Why can die placement error matter before RDL patterning?","options":["A molded surface automatically corrects all coordinates","Redistribution carries no current","The later routing must land on the actual die-pad positions"],"answer":2,"explanation":"Geometric mismatch between planned routes and real pads can cause opens or shorts even if each die itself is good."},"science":[{"title":"Registration budget","equation":"e_total² ≈ e_place² + e_pattern² + e_distortion²","explanation":"Each e is a standard-deviation-like alignment contribution in the same length unit.","assumptions":"Root-sum-square model only for independent zero-mean contributions. Systematic offsets must be corrected or budgeted explicitly."}],"prerequisites":["flip-chip-abf-substrate","wafer-handling-genealogy"],"learningObjective":"Explain RDL function and why fan-out route order affects alignment.","workstream":"W05","visualFamily":"package-route","engineeringExample":"Synthetic independent alignment terms of 2, 1 and 2 μm combine to 3 μm RMS. If the 2 μm placement term is systematic, averaging more measurements does not erase its physical offset.","evidenceNotes":"The lesson shows a generic reconstruction sequence, not a vendor’s complete fan-out recipe or qualified alignment budget.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}