Edge-triggered D flip-flop

The mechanism

Combinational logic responds to its present inputs; sequential logic also carries state. A D flip-flop samples its data input around an active clock edge and holds the resulting output until a later capture. Internal feedback makes storage possible, while clock-controlled structures regulate when changes propagate. Data must satisfy setup and hold requirements, and the output appears after clock-to-output delay. These are physical timing constraints rather than perfectly instantaneous events. The atlas displays data, clock, and stored state separately so a viewer can watch an arithmetic result become the next stage's input. A register is a collection of such stored bits, often with additional enable and reset behavior.

Present stable data during the required interval around a capture edge.
Use clock-controlled internal structures to capture the state.
Hold the output through the next combinational evaluation until another permitted capture.

Science and assumptions

Setup-constrained clock period

T_{\mathrm{clock}}\ge t_{CQ,\max}+t_{\mathrm{logic},\max}+t_{\mathrm{setup}}+t_{\mathrm{uncertainty}}

The clock period must cover maximum clock-to-Q delay, maximum logic delay, setup time and the uncertainty budget.

Symbols and units

T_clock: Available clock period
s
t_CQ,max: Maximum launch register clock-to-Q delay
s
t_logic,max: Maximum combinational path delay
s
t_setup: Capture register setup time
s
t_uncertainty: Conservative nonnegative clock uncertainty budget
s

Data must leave the first register, traverse combinational logic, and settle before the next capture. This sets a lower bound on the cycle time for a path.

Assumptions Single-cycle synchronous path with conservative nonnegative clock uncertainty; hold constraints and multi-cycle exceptions are separate checks.

Engineering example

Synthetic path: 40 ps clock-to-Q + 120 ps logic + 30 ps setup + 10 ps uncertainty requires a period of at least 200 ps. Its setup-only frequency ceiling is 1/(200 ps) = 5 GHz. A passing setup sum does not establish that the hold constraint passes.

Distinctions and tradeoffs

A clock edge is not an infinitely precise instant with no constraints; setup, hold, and clock-to-output timing matter.

More pipeline stages can shorten combinational paths. Extra state and clock load consume area and power.

Flip-flops coordinate arithmetic and control over time. They let many operations occupy different pipeline stages simultaneously.

Specifications and interfaces

Stored information: 1 bit
An elementary D flip-flop.
Capture conditions: Setup and hold
Input timing requirements around the active edge.
Pipeline boundary: Clock-to-Q delay
Output does not change instantaneously.

Interfaces

D and clock Input: Data and capture timing
Q Output: Retained state bit

Check your understanding

What distinguishes a flip-flop from combinational logic?

It computes without electrical power
It retains state between capture events
It contains no transistors

Answer and reasoning

It retains state between capture events

Stored state connects one stage of time to the next. Combinational logic instead derives outputs from its current inputs.

Evidence and scope

The timing budget follows the linked sequential-logic lecture. These are synthetic maximum-delay values for one synchronous path; clock skew, hold timing, variation and path exceptions need separate checks.

Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.