The mechanism
A two-input NAND outputs zero only when both inputs are one. Its standard static CMOS network uses series nMOS devices to pull down when both conditions are true and parallel pMOS devices to pull up otherwise. This relationship between series, parallel, and logic is the bridge from circuit topology to a truth table. NAND is universal: networks of NAND gates can represent any Boolean function, although practical chips use many cell types for efficiency. The atlas lets a viewer trace the conducting path for each input combination. Four visible devices are enough to explain the function, while the circuit's delay still depends on physical loads and transistor choices.
- Use two series nMOS devices for the path from output to ground.
- Use the complementary parallel pMOS network for the path toward the supply.
- Evaluate input combinations: only two high inputs complete the pull-down condition.
Science and assumptions
Boolean function from topology
The output is the logical negation of A AND B: it is low only when both inputs are high.
Symbols and units
- Y
- NAND output logic value
Boolean
- A
- First input logic value
Boolean
- B
- Second input logic value
Boolean
Series pull-down devices implement the requirement that both inputs be high. Their complementary parallel pull-up network produces the opposite output state.
Assumptions Ideal logic values within valid input/output voltage ranges; real transition timing and analog current are omitted.
Engineering example
Worked ideal truth table: inputs 00, 01 and 10 each leave at least one pull-up conducting and produce Y = 1. Input 11 enables the complete series pull-down and produces Y = 0. Thus three of the four input combinations produce a high output.
Distinctions and tradeoffs
NAND universality means networks can express any Boolean function; it does not mean one NAND gate performs every computation.
Series devices add resistance to a conducting path. More complex cells trade transistor count against logic depth.
NAND networks help implement control and arithmetic. Their composition explains how a few switching patterns scale into computation.
Specifications and interfaces
- Logic equation
- Y = NOT(A AND B)
Output is low only for A = B = 1.
- Canonical implementation
- 4 transistors
Two nMOS and two pMOS.
- Logical property
- Universal gate
Networks can express arbitrary Boolean functions.
Interfaces
- A and B Input
- Two binary-encoded voltage inputs
- Y Output
- NAND output voltage
Check your understanding
When is a two-input NAND output zero?
- Only when both inputs are one
- Whenever either input is zero
- For all input combinations
Answer and reasoning
Only when both inputs are one
The series pull-down devices conduct together for the two-high case, implementing NOT(A AND B).
Evidence and scope
This is ideal Boolean reasoning within valid voltage ranges, using the linked computation-structures treatment. It does not predict transition current, delay or simultaneous conduction.
Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.