{"id":"flipflop","level":"logic","name":"Edge-triggered D flip-flop","shortName":"Flip-flop","role":"Captures a bit at a clock event and retains it for the next computation stage.","description":"Combinational logic responds to its present inputs; sequential logic also carries state. A D flip-flop samples its data input around an active clock edge and holds the resulting output until a later capture. Internal feedback makes storage possible, while clock-controlled structures regulate when changes propagate. Data must satisfy setup and hold requirements, and the output appears after clock-to-output delay. These are physical timing constraints rather than perfectly instantaneous events. The atlas displays data, clock, and stored state separately so a viewer can watch an arithmetic result become the next stage's input. A register is a collection of such stored bits, often with additional enable and reset behavior.","specs":[{"label":"Stored information","value":"1 bit","context":"An elementary D flip-flop."},{"label":"Capture conditions","value":"Setup and hold","context":"Input timing requirements around the active edge."},{"label":"Pipeline boundary","value":"Clock-to-Q delay","context":"Output does not change instantaneously."}],"interfaces":[{"name":"D and clock","direction":"in","signal":"Data and capture timing"},{"name":"Q","direction":"out","signal":"Retained state bit"}],"tradeoff":"More pipeline stages can shorten combinational paths. Extra state and clock load consume area and power.","whyAI":"Flip-flops coordinate arithmetic and control over time. They let many operations occupy different pipeline stages simultaneously.","related":["clock","adder","mac","standard-cell"],"sources":[{"title":"MIT 6.111 — Sequential Logic and System Timing","url":"https://ocw.mit.edu/courses/6-111-introductory-digital-systems-laboratory-spring-2006/31134a27ec1bedf570a26922790dfbec_lec11.pdf"}],"scale":"Microscopic sequential cell; timing diagram is conceptual","kind":"flipflop","mechanism":["Present stable data during the required interval around a capture edge.","Use clock-controlled internal structures to capture the state.","Hold the output through the next combinational evaluation until another permitted capture."],"misconception":"A clock edge is not an infinitely precise instant with no constraints; setup, hold, and clock-to-output timing matter.","check":{"question":"What distinguishes a flip-flop from combinational logic?","options":["It computes without electrical power","It retains state between capture events","It contains no transistors"],"answer":1,"explanation":"Stored state connects one stage of time to the next. Combinational logic instead derives outputs from its current inputs."},"branch":"Digital circuits","subbranch":"Sequential timing","science":[{"title":"Setup-constrained clock period","equation":"T_clock ≥ t_CQ,max + t_logic,max + t_setup + t_uncertainty","explanation":"Data must leave the first register, traverse combinational logic, and settle before the next capture. This sets a lower bound on the cycle time for a path.","assumptions":"Single-cycle synchronous path with conservative nonnegative clock uncertainty; hold constraints and multi-cycle exceptions are separate checks."}],"history":[],"prerequisites":["inverter","nand"],"learningObjective":"Combine register and logic delays into a setup timing budget while keeping hold checks separate.","engineeringExample":"Synthetic path: 40 ps clock-to-Q + 120 ps logic + 30 ps setup + 10 ps uncertainty requires a period of at least 200 ps. Its setup-only frequency ceiling is 1/(200 ps) = 5 GHz. A passing setup sum does not establish that the hold constraint passes.","evidenceNotes":"The timing budget follows the linked sequential-logic lecture. These are synthetic maximum-delay values for one synchronous path; clock skew, hold timing, variation and path exceptions need separate checks.","labId":"library","scope":"Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.","investigationId":"switching","labScope":"Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism."}