The mechanism
A wafer start is not a good die. The wafer geometry first limits how many complete die sites fit, then process defects and electrical specifications determine which sites are usable. Random defects, repeating layout weaknesses and spatial process variation generate different wafer-map patterns. A simple random-defect model is useful for understanding area sensitivity, but it cannot explain every loss mechanism or replace measured yield. Redundancy and binning can also make “good” depend on the product definition. This lesson follows a count from gross sites to tested bins and preserves the population at each stage before linking it to package supply.
- Count complete die sites using the actual usable wafer boundary and die/street geometry.
- Distinguish defects likely to kill a die from noncritical inspection findings.
- Compare random-defect expectations with spatial, repeating and parametric loss patterns.
- Apply the defined electrical tests, redundancy rules and product bin criteria.
- Report good output with explicit denominators and retain the wafer map for assembly genealogy.
Science and assumptions
Random killer-defect model
Independent Poisson fatal-defect survival is the exponential of minus defect density times effective die area.
Symbols and units
- Y
- Survival probability under the fatal-defect model
fraction
- D₀
- Uniform fatal-defect density
cm⁻²
- A
- Effective die area
cm²
Y is dimensionless die survival probability; D₀ is killer-defect density per cm² and A die area in cm².
Assumptions Independent spatial Poisson defects, each fatal within effective area. Clustering, redundancy, systematic and parametric failures violate this simple model.
Engineering example
Synthetic example: D₀ = 0.1 cm⁻² and A = 4 cm² give Y ≈ 0.670. A gross count of 100 complete sites then predicts 67 survivors under this model, before separately scoped losses.
Distinctions and tradeoffs
A Poisson yield curve is not a measured foundry yield or an explanation of every wafer-map pattern.
Larger dies can integrate more function but expose more area to defects and reduce gross dies per wafer.
Accelerator supply depends on good die count and usable bins, not only wafer starts or the number of transistors drawn.
Specifications and interfaces
- Yield denominator
- Good dies / defined tested or gross population
Specify whether untested, partial and excluded sites are included.
- Defect density
- Killer defects per area
A model input, distinct from every optically detected feature.
Interfaces
- Wafer geometry and process data Input
- Complete sites, defect information and electrical criteria
- Good-die population Output
- Traceable bins for assembly or further screening
Check your understanding
Why can two dies of equal area have different yield?
- Testing creates identical transistors
- Layout sensitivity, defect exposure and electrical requirements can differ
- Equal area guarantees equal yield
Answer and reasoning
Layout sensitivity, defect exposure and electrical requirements can differ
Area is only one input; design and process populations determine which defects and variations are fatal.
Evidence and scope
Numbers are synthetic. Never multiply an already measured finished-output yield by the same defect loss again.
Explore gross sites and random-defect survival; geometric approximations and defect models do not replace wafer test.