{"id":"yield-wafer-defect-model","level":"die","name":"Wafer maps and good-die yield","shortName":"Wafer maps and good-die yield","role":"Separates geometrical die count, defects, electrical limits and screened output.","description":"A wafer start is not a good die. The wafer geometry first limits how many complete die sites fit, then process defects and electrical specifications determine which sites are usable. Random defects, repeating layout weaknesses and spatial process variation generate different wafer-map patterns. A simple random-defect model is useful for understanding area sensitivity, but it cannot explain every loss mechanism or replace measured yield. Redundancy and binning can also make “good” depend on the product definition. This lesson follows a count from gross sites to tested bins and preserves the population at each stage before linking it to package supply.","specs":[{"label":"Yield denominator","value":"Good dies / defined tested or gross population","context":"Specify whether untested, partial and excluded sites are included."},{"label":"Defect density","value":"Killer defects per area","context":"A model input, distinct from every optically detected feature."}],"interfaces":[{"name":"Wafer geometry and process data","direction":"in","signal":"Complete sites, defect information and electrical criteria"},{"name":"Good-die population","direction":"out","signal":"Traceable bins for assembly or further screening"}],"tradeoff":"Larger dies can integrate more function but expose more area to defects and reduce gross dies per wafer.","whyAI":"Accelerator supply depends on good die count and usable bins, not only wafer starts or the number of transistors drawn.","related":["silicon-wafer","known-good-die-test","hbm-silicon-intensity"],"sources":[{"title":"KLA — Chip Manufacturing 101","url":"https://www.kla.com/wp-content/uploads/ChipManufacturing101.pdf"},{"title":"KLA — Practical Applications of Measurement System Analysis","url":"https://www.kla.com/documents/5.3_Practical_Applications_of_MSA_Sutherland_KLA.pdf"},{"title":"Advantest — Semiconductor test glossary","url":"https://www.advantest.com/en/investors/ir-library/glossary/"}],"scale":"Feature measurements, wafer maps and time-dependent production","kind":"process","branch":"Fabrication / Control, test and ramp","subbranch":"From processed wafers to released output","mechanism":["Count complete die sites using the actual usable wafer boundary and die/street geometry.","Distinguish defects likely to kill a die from noncritical inspection findings.","Compare random-defect expectations with spatial, repeating and parametric loss patterns.","Apply the defined electrical tests, redundancy rules and product bin criteria.","Report good output with explicit denominators and retain the wafer map for assembly genealogy."],"misconception":"A Poisson yield curve is not a measured foundry yield or an explanation of every wafer-map pattern.","check":{"question":"Why can two dies of equal area have different yield?","options":["Testing creates identical transistors","Layout sensitivity, defect exposure and electrical requirements can differ","Equal area guarantees equal yield"],"answer":1,"explanation":"Area is only one input; design and process populations determine which defects and variations are fatal."},"science":[{"title":"Random killer-defect model","equation":"Y = exp(−D₀A)","explanation":"Y is dimensionless die survival probability; D₀ is killer-defect density per cm² and A die area in cm².","assumptions":"Independent spatial Poisson defects, each fatal within effective area. Clustering, redundancy, systematic and parametric failures violate this simple model."}],"prerequisites":["wafer-finishing-geometry","fab-metrology-process-window"],"learningObjective":"Distinguish gross die count, model yield and tested usable output.","workstream":"W04","visualFamily":"fab-operations","engineeringExample":"Synthetic example: D₀ = 0.1 cm⁻² and A = 4 cm² give Y ≈ 0.670. A gross count of 100 complete sites then predicts 67 survivors under this model, before separately scoped losses.","evidenceNotes":"Numbers are synthetic. Never multiply an already measured finished-output yield by the same defect loss again.","labId":"engineering","scope":"Explore gross sites and random-defect survival; geometric approximations and defect models do not replace wafer test.","deepLabId":"wafer","investigationId":"manufacturing","labScope":"Explore gross sites and random-defect survival; geometric approximations and defect models do not replace wafer test."}