The mechanism
An unsigned binary multiplier starts with partial products formed from pairs of operand bits. Each partial product has a binary position, so the hardware must combine aligned contributions and carries. An array or reduction tree organizes that work; a final addition resolves the remaining result. Signed and floating-point multiplication require additional representation-specific machinery beyond this teaching example. The atlas arranges partial products in a shifted grid and highlights their reduction paths, revealing why multiplication has more structure than one isolated gate. Pipeline registers may separate stages so several products are in flight together. The shown four-bit example is deliberately small enough to inspect while preserving the dependency pattern of wider arithmetic.
- Generate bit-pair partial products at their proper binary positions.
- Reduce the aligned contributions through an array or tree of arithmetic logic.
- Use final addition and representation handling to obtain the product.
Science and assumptions
Binary product expansion
An unsigned binary product is the sum of every bit-pair product weighted by two raised to the sum of the bit positions.
Symbols and units
- A
- First unsigned binary operand
integer
- B
- Second unsigned binary operand
integer
- aᵢ
- Bit i of A
0 or 1
- bⱼ
- Bit j of B
0 or 1
- i,j
- Finite operand bit positions
nonnegative integer indices
Each pair of input bits contributes a weighted partial product. The array or tree reduces these contributions into the final binary result.
Assumptions Unsigned finite binary operands; signed encodings and floating-point arithmetic require additional transformations.
Engineering example
Worked multiplication: 0101₂ × 0011₂ forms 00000101₂ and 00001010₂ from the two set bits of the multiplier. Adding them gives 00001111₂ = 15. Four-bit unsigned operands need up to eight result bits because 15 × 15 = 225.
Distinctions and tradeoffs
The four-by-four partial-product example is not a claim about a commercial accelerator’s internal arithmetic width.
Parallel reduction improves throughput and delay. Wider arithmetic increases area, wiring, and switching activity.
Multiplication is central to neural-network linear algebra. Its physical cost helps motivate lower-precision formats when accuracy permits.
Specifications and interfaces
- Teaching operands
- 4 bits × 4 bits
Unsigned illustrative example.
- Full result width
- Up to 8 bits
Exact product of two four-bit unsigned values.
- Core pattern
- Partial products → reduction → sum
Specific architectures choose different reductions.
Interfaces
- Two operands Input
- Binary-encoded numbers
- Product Output
- Weighted combination of partial products
Check your understanding
How wide can the full unsigned result of 4-bit × 4-bit multiplication be?
- 4 bits in every case
- 8 bits
- 16 bytes in every case
Answer and reasoning
8 bits
The maximum product is 15 × 15 = 225, which requires eight bits to represent exactly.
Evidence and scope
This is the unsigned partial-product construction in the linked multiplier lecture. Signed encodings, floating-point normalization and circuit timing require additional rules.
Inspect row–column products and accumulated results in a small integer matrix; this does not simulate the individual gate network.