HBM layer count and physical height

The mechanism

An HBM stack is assembled from separately fabricated DRAM dies and a base/interface structure. “12-high” describes a specified count of memory dies; it is neither twelve transistors nor a height in micrometers. Within a mechanical envelope, adding layers requires redistributing the thickness budget among silicon, inter-die joints, base structures and clearance. Wafer thinning and TSV reveal make vertical electrical paths accessible, but thin dies are harder to handle without bow or damage. Capacity rises with the number of usable bits in the memory dies. External bandwidth is set by the interface and achievable data rate, so more dies do not automatically create more external signal wires.

Begin with tested memory wafers and identify whether each drawing counts memory dies or the base die.
Thin on a compatible carrier; measure total thickness variation, warp and TSV reveal before handling the separated dies.
Allocate a mechanical budget to the base, every silicon layer, every counted bond line and the top allowance.
Verify that pad positions, channels, thermal path and package interfaces remain compatible as the layer count changes.
Test the assembled stack and report capacity, bandwidth and physical height as three separate outcomes.

Science and assumptions

Stack-height budget

H=t_{\mathrm{base}}+N t_{\mathrm{die}}+J t_{\mathrm{bond}}+t_{\mathrm{cap}}

H = tbase + N tdie + J tbond + tcap

Symbols and units

H: Modeled stack height
µm
tbase: Base structure thickness
µm
N: Number of memory dies
count
tdie: Memory die thickness
µm
J: Counted bond lines
count
tbond: Thickness per bond line
µm
tcap: Top allowance in this model
µm

Count each physical thickness once. J includes every bond line represented in this cross-section; its value depends on whether the base interface is included.

Assumptions Uniform die/bond thickness is a teaching simplification. Real layouts include local steps, tolerances and route-specific top structures.

Capacity is not bandwidth

C=N C_{\mathrm{die}},\qquad B=\frac{w r\eta}{8}

C = N Cdie; B = w r η / 8

Symbols and units

C: Stack capacity
bytes
Cdie: Usable capacity per memory die
bytes
w: Number of data bits transferred in parallel
bits/transfer
r: Transfers per second per data pin
transfers/s
η: Payload efficiency
fraction
B: Usable interface bandwidth
bytes/s
N: Number of memory dies
count

Capacity C counts bytes; bandwidth B counts delivered bytes each second across the stated interface.

Assumptions Equal capacity dies; data rate r already counts transfers; usable efficiency must be stated.

Engineering example

Synthetic budget: base 60 µm, 12 memory dies × 30 µm, 12 included joints × 7 µm and a 40 µm allowance give 544 µm. Changing die thickness to 40 µm gives 664 µm. These are arithmetic inputs, not a JEDEC height limit or product cross-section.

Distinctions and tradeoffs

Die count, silicon thickness and the external interface are separate design variables.

Thinner silicon frees vertical space while increasing handling sensitivity; smaller joints demand tighter assembly control.

A larger working set can fit locally without a proportional increase in external memory bandwidth.

Specifications and interfaces

Layer count: Memory dies, separately from base
Read each product drawing’s counting convention.
Height budget: Silicon + joints + base + allowance
A die-count label is not a dimensional drawing.

Interfaces

TSV reveal Input: Exposed vertical conductors and measured silicon thickness
Accelerator package Output: Stack height, interface footprint and thermal contact

Check your understanding

A stack changes from 8 to 12 memory dies at unchanged external width and pin rate. What follows directly?

Capacity can rise; external peak bandwidth need not change
External bandwidth must rise by 50%
Physical height must rise by 50%

Answer and reasoning

Capacity can rise; external peak bandwidth need not change

Die count, silicon thickness and the external interface are separate design variables.

Evidence and scope

SK hynix’s 2023 account describes fitting more DRAM dies into the same height through thinner dies and changed assembly. The source supports the mechanism; the lab uses independent illustrative dimensions.

Adjust stack layers, thickness, joint route, interface bandwidth and conditional yield; presets are synthetic, not supplier process windows.