{"id":"hbm-stack-height-budget","level":"package","name":"HBM layer count and physical height","shortName":"HBM layer count and physical height","role":"Separate memory-die count, package thickness, stored bits and interface bandwidth.","description":"An HBM stack is assembled from separately fabricated DRAM dies and a base/interface structure. “12-high” describes a specified count of memory dies; it is neither twelve transistors nor a height in micrometers. Within a mechanical envelope, adding layers requires redistributing the thickness budget among silicon, inter-die joints, base structures and clearance. Wafer thinning and TSV reveal make vertical electrical paths accessible, but thin dies are harder to handle without bow or damage. Capacity rises with the number of usable bits in the memory dies. External bandwidth is set by the interface and achievable data rate, so more dies do not automatically create more external signal wires.","mechanism":["Begin with tested memory wafers and identify whether each drawing counts memory dies or the base die.","Thin on a compatible carrier; measure total thickness variation, warp and TSV reveal before handling the separated dies.","Allocate a mechanical budget to the base, every silicon layer, every counted bond line and the top allowance.","Verify that pad positions, channels, thermal path and package interfaces remain compatible as the layer count changes.","Test the assembled stack and report capacity, bandwidth and physical height as three separate outcomes."],"science":[{"title":"Stack-height budget","equation":"H = tbase + N tdie + J tbond + tcap","explanation":"Count each physical thickness once. J includes every bond line represented in this cross-section; its value depends on whether the base interface is included.","assumptions":"Uniform die/bond thickness is a teaching simplification. Real layouts include local steps, tolerances and route-specific top structures."},{"title":"Capacity is not bandwidth","equation":"C = N Cdie; B = w r η / 8","explanation":"Capacity C counts bytes; bandwidth B counts delivered bytes each second across the stated interface.","assumptions":"Equal capacity dies; data rate r already counts transfers; usable efficiency must be stated."}],"specs":[{"label":"Layer count","value":"Memory dies, separately from base","context":"Read each product drawing’s counting convention."},{"label":"Height budget","value":"Silicon + joints + base + allowance","context":"A die-count label is not a dimensional drawing."}],"interfaces":[{"name":"TSV reveal","direction":"in","signal":"Exposed vertical conductors and measured silicon thickness"},{"name":"Accelerator package","direction":"out","signal":"Stack height, interface footprint and thermal contact"}],"tradeoff":"Thinner silicon frees vertical space while increasing handling sensitivity; smaller joints demand tighter assembly control.","whyAI":"A larger working set can fit locally without a proportional increase in external memory bandwidth.","prerequisites":["hbm-tsv-reveal","temporary-carrier-thinning"],"related":["hbm-stack-thermal-yield","hbm-bonding-process-selection","hbm-channel-generation-ras"],"misconception":"Die count, silicon thickness and the external interface are separate design variables.","check":{"question":"A stack changes from 8 to 12 memory dies at unchanged external width and pin rate. What follows directly?","options":["Capacity can rise; external peak bandwidth need not change","External bandwidth must rise by 50%","Physical height must rise by 50%"],"answer":0,"explanation":"Die count, silicon thickness and the external interface are separate design variables."},"engineeringExample":"Synthetic budget: base 60 µm, 12 memory dies × 30 µm, 12 included joints × 7 µm and a 40 µm allowance give 544 µm. Changing die thickness to 40 µm gives 664 µm. These are arithmetic inputs, not a JEDEC height limit or product cross-section.","evidenceNotes":"SK hynix’s 2023 account describes fitting more DRAM dies into the same height through thinner dies and changed assembly. The source supports the mechanism; the lab uses independent illustrative dimensions.","sources":[{"title":"SK hynix — the team behind 12-layer HBM3","url":"https://news.skhynix.com/en/meet-the-sk-hynix-team-behind-the-worlds-first-12-layer-hbm3/"},{"title":"Samsung — 36 GB HBM3E 12H development","url":"https://news.samsung.com/global/samsung-develops-industry-first-36gb-hbm3e-12h-dram"}],"learningObjective":"Separate memory-die count, package thickness, stored bits and interface bandwidth.","workstream":"W06","visualFamily":"hbm-detail","scale":"Die micrometers → assembled stack; vertical geometry exaggerated","kind":"process","labId":"hbm-stack-build","branch":"Memory","subbranch":"HBM height, heat and test closure","scope":"Adjust stack layers, thickness, joint route, interface bandwidth and conditional yield; presets are synthetic, not supplier process windows.","investigationId":"manufacturing","labScope":"Adjust stack layers, thickness, joint route, interface bandwidth and conditional yield; presets are synthetic, not supplier process windows."}