Fin field-effect transistor

The mechanism

A FinFET lifts the semiconductor channel into a narrow vertical fin. In a common tri-gate realization, the gate crosses the fin and controls the two sidewalls and the top surface. That geometry gives stronger electrostatic control than a gate acting only from above a thick planar body. Adding fins can increase effective drive width, so the number and dimensions of fins become design choices rather than decorative repetition. The atlas compares a planar channel and fin channel at matched conceptual scale. It does not assign a modern process-node label to a measured gate length. The important visual change is how much of the conducting body lies close to a controlling gate.

Raise a thin semiconductor fin above its surroundings.
Wrap a common tri-gate around the fin’s top and two sides.
Use the closer gate coverage to improve control over channel conduction.

Science and assumptions

Effective gated width

W_{\mathrm{eff}}\approx N_{\mathrm{fin}}(2H_{\mathrm{fin}}+W_{\mathrm{fin}})

Effective tri-gate width is approximately fin count times twice the fin height plus its top width.

Symbols and units

W_eff: Total geometric gated width
nm
N_fin: Number of fins
count
H_fin: Gated fin sidewall height
nm
W_fin: Gated fin top width
nm

A tri-gated rectangular fin contributes two sidewall heights and its top width. Multiple fins add parallel gated perimeter, explaining discrete drive-width choices.

Assumptions Geometric approximation for a tri-gate with comparable surface conduction; double-gate devices and real mobility/corner effects differ.

Engineering example

Adding one identical fin increases the idealized effective width by roughly 2H_fin+ $W_{\mathrm{fin}}$ ; variability and quantized layout remain.

Distinctions and tradeoffs

A FinFET’s multiple controlled surfaces do not mean it has three independent logical gates.

Three-dimensional control helps suppress leakage. Fin geometry constrains drive choices and manufacturing tolerances.

FinFETs enabled dense CMOS generations used in accelerators. They improve the physical switches beneath software-level parallelism.

Specifications and interfaces

Common gate coverage: Two sides plus top
Tri-gate FinFET example; other multigate variants exist.
Width control: Fin count and dimensions
Discrete fins affect available drive strength.
Historical milestone: Intel announcement, 2011
22 nm process generation; node name is not a scale ruler.

Interfaces

Gate voltage Input: Field over multiple channel surfaces
Fin channel Output: Controlled source–drain conduction

Check your understanding

What does the fin mainly improve?

Electrostatic gate control over the channel body
The number of software layers in the model
The accuracy of a neural network without training

Answer and reasoning

Electrostatic gate control over the channel body

Fin geometry places more of the channel close to the gate. Any AI benefit arises through circuit-level hardware performance.

Historical context

2011 · Intel announces 3D Tri-Gate for the 22 nm generation

Multisurface gate control moved a major production logic platform beyond planar transistor geometry. This is an Intel commercialization milestone, not the first invention of every FinFET concept.

Intel — Three-Dimensional Tri-Gate Announcement

Evidence and scope

The expression omits fin corners, mobility variation, parasitic resistance and layout rules.

Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.