{"id":"finfet","level":"transistor","name":"Fin field-effect transistor","shortName":"FinFET","role":"Raises the channel into a fin so the gate controls multiple surfaces.","description":"A FinFET lifts the semiconductor channel into a narrow vertical fin. In a common tri-gate realization, the gate crosses the fin and controls the two sidewalls and the top surface. That geometry gives stronger electrostatic control than a gate acting only from above a thick planar body. Adding fins can increase effective drive width, so the number and dimensions of fins become design choices rather than decorative repetition. The atlas compares a planar channel and fin channel at matched conceptual scale. It does not assign a modern process-node label to a measured gate length. The important visual change is how much of the conducting body lies close to a controlling gate.","specs":[{"label":"Common gate coverage","value":"Two sides plus top","context":"Tri-gate FinFET example; other multigate variants exist."},{"label":"Width control","value":"Fin count and dimensions","context":"Discrete fins affect available drive strength."},{"label":"Historical milestone","value":"Intel announcement, 2011","context":"22 nm process generation; node name is not a scale ruler."}],"interfaces":[{"name":"Gate voltage","direction":"in","signal":"Field over multiple channel surfaces"},{"name":"Fin channel","direction":"out","signal":"Controlled source–drain conduction"}],"tradeoff":"Three-dimensional control helps suppress leakage. Fin geometry constrains drive choices and manufacturing tolerances.","whyAI":"FinFETs enabled dense CMOS generations used in accelerators. They improve the physical switches beneath software-level parallelism.","related":["mosfet","channel","gaa","standard-cell"],"sources":[{"title":"Intel — Three-Dimensional Tri-Gate Transistors, 2011","url":"https://www.intc.com/news-events/press-releases/detail/655/intel-reinvents-transistors-using-new-3-d-structure"},{"title":"Intel — Process Technology Naming","url":"https://www.intel.com/content/www/us/en/support/articles/000097598/processors.html"},{"title":"Original Device Study — Effective Fin Width and FinFET Geometry","url":"https://www.mdpi.com/2079-9292/11/1/91"}],"scale":"Nanometer-scale fin; node labels are technology names","kind":"finfet","mechanism":["Raise a thin semiconductor fin above its surroundings.","Wrap a common tri-gate around the fin’s top and two sides.","Use the closer gate coverage to improve control over channel conduction."],"misconception":"A FinFET’s multiple controlled surfaces do not mean it has three independent logical gates.","check":{"question":"What does the fin mainly improve?","options":["Electrostatic gate control over the channel body","The number of software layers in the model","The accuracy of a neural network without training"],"answer":0,"explanation":"Fin geometry places more of the channel close to the gate. Any AI benefit arises through circuit-level hardware performance."},"branch":"Device architectures","subbranch":"Fin channels","science":[{"title":"Effective gated width","equation":"W_eff ≈ N_fin(2H_fin + W_fin)","explanation":"A tri-gated rectangular fin contributes two sidewall heights and its top width. Multiple fins add parallel gated perimeter, explaining discrete drive-width choices.","assumptions":"Geometric approximation for a tri-gate with comparable surface conduction; double-gate devices and real mobility/corner effects differ."}],"history":[{"year":2011,"title":"Intel announces 3D Tri-Gate for the 22 nm generation","significance":"Multisurface gate control moved a major production logic platform beyond planar transistor geometry. This is an Intel commercialization milestone, not the first invention of every FinFET concept.","source":{"title":"Intel — Three-Dimensional Tri-Gate Announcement","url":"https://www.intc.com/news-events/press-releases/detail/655/intel-reinvents-transistors-using-new-3-d-structure"}}],"learningObjective":"Compare fin count and fin geometry as effective width.","engineeringExample":"Adding one identical fin increases the idealized effective width by roughly 2H_fin+W_fin; variability and quantized layout remain.","evidenceNotes":"The expression omits fin corners, mobility variation, parasitic resistance and layout rules.","visualFamily":"device-crosssection","prerequisites":["mosfet","gate-stack"],"labId":"library","scope":"Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.","investigationId":"switching","labScope":"Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism."}