The mechanism
Every physical implementation communicates: gates exchange signals, memories exchange addresses and data, dies exchange packets, and systems exchange work and checkpoints. The computation-realization graph treats these transfers as first-class objects with source, destination, encoding, rate, latency, energy and error conditions. This makes data movement visible beside arithmetic. It also explains why communication theory is useful to chip design: a representation is only operational when a receiver can distinguish it within the available noise, timing and power margins. The graph can be refined from a conceptual edge to a routed wire or protocol transaction without changing its teaching role.
- Represent a computational dependency as a producer-to-consumer edge.
- Assign an encoding and distinguishability condition to the edge.
- Add rate, latency, energy and error budgets at the chosen boundary.
- Map logical edges to physical paths, buffers, interfaces and protocols.
- Measure delivered useful information rather than nominal link capacity.
Science and assumptions
A communication edge
Edge time is startup latency plus transferred bits divided by effective bit bandwidth. Edge energy is transferred bits times effective joules per bit.
M is bits in both relations. If a payload is given in bytes, convert it before combining it with bit bandwidth or joules per bit; the energy term omits any separately unaccounted startup energy.
Symbols and units
- t_edge
- Modeled edge communication time
s
- α
- Fixed edge startup latency
s
- M
- Bits transferred at the defined edge boundary
bits
- β
- Effective bit-transfer bandwidth at that boundary
bits/s
- E_edge
- Modeled energy associated with those transferred bits
J
- e_bit
- Effective energy per transferred bit under the stated convention
J/bit
A simple edge model separates startup latency α from payload transfer M/β and scales energy with transferred bits and an effective energy-per-bit term.
Assumptions Homogeneous effective bandwidth and energy; protocol overhead, contention and topology require additional terms.
Engineering example
For a 1 GB collective payload over a 100 GB/s effective path with 5 μs startup, the payload term is about 10 ms; a topology or contention change can dominate the same arithmetic operation.
Distinctions and tradeoffs
A link labeled high bandwidth does not guarantee useful workload throughput when latency, contention, serialization or receiver capacity binds.
More communication can improve locality or redundancy while increasing wires, buffers, power and verification surface.
Attention, all-reduce, KV-cache traffic and checkpointing are communication graphs whose edges can bind an AI system before arithmetic does.
Specifications and interfaces
- Edge fields
- Payload, encoding, rate, latency, energy, error
Values require a declared boundary and time period.
- Node fields
- State, storage, transform or control
A node may be logical or physical; the model labels the abstraction.
Interfaces
- State producer Input
- Encoded data, control or measurement
- State receiver Output
- Accepted data with timing and error conditions
Check your understanding
Why does the CRG include communication beside computation?
- Because arithmetic never consumes energy
- Because physical states must be transferred and distinguished between operations
- Because all chips use the same network topology
Answer and reasoning
Because physical states must be transferred and distinguished between operations
The receiver and the path are part of a physical implementation of a computation.
Evidence and scope
The edge equation is a bounded teaching model. Shannon’s source addresses communication limits; it does not by itself specify a chip architecture.
Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.