{"id":"crg-communication-graph","level":"system","name":"Communication is the realization medium","shortName":"Communication graph","role":"Maps computational state, data movement and control into a graph of physical interfaces.","description":"Every physical implementation communicates: gates exchange signals, memories exchange addresses and data, dies exchange packets, and systems exchange work and checkpoints. The computation-realization graph treats these transfers as first-class objects with source, destination, encoding, rate, latency, energy and error conditions. This makes data movement visible beside arithmetic. It also explains why communication theory is useful to chip design: a representation is only operational when a receiver can distinguish it within the available noise, timing and power margins. The graph can be refined from a conceptual edge to a routed wire or protocol transaction without changing its teaching role.","specs":[{"label":"Edge fields","value":"Payload, encoding, rate, latency, energy, error","context":"Values require a declared boundary and time period."},{"label":"Node fields","value":"State, storage, transform or control","context":"A node may be logical or physical; the model labels the abstraction."}],"interfaces":[{"name":"State producer","direction":"in","signal":"Encoded data, control or measurement"},{"name":"State receiver","direction":"out","signal":"Accepted data with timing and error conditions"}],"tradeoff":"More communication can improve locality or redundancy while increasing wires, buffers, power and verification surface.","whyAI":"Attention, all-reduce, KV-cache traffic and checkpointing are communication graphs whose edges can bind an AI system before arithmetic does.","related":["crg-problem-statement","on-chip-network","nvlink-port","nccl"],"sources":[{"title":"Semi AI Foundry — Communication Theory of Computation Realization","url":"https://semiaifoundry.com/updates/communication-theory-of-computation-realization/"},{"title":"Claude Shannon — A Mathematical Theory of Communication","url":"https://people.math.harvard.edu/~ctm/home/text/others/shannon/entropy/entropy.pdf"}],"scale":"Signal, wire, link, fabric and workload graph","kind":"theory","mechanism":["Represent a computational dependency as a producer-to-consumer edge.","Assign an encoding and distinguishability condition to the edge.","Add rate, latency, energy and error budgets at the chosen boundary.","Map logical edges to physical paths, buffers, interfaces and protocols.","Measure delivered useful information rather than nominal link capacity."],"misconception":"A link labeled high bandwidth does not guarantee useful workload throughput when latency, contention, serialization or receiver capacity binds.","check":{"question":"Why does the CRG include communication beside computation?","options":["Because arithmetic never consumes energy","Because physical states must be transferred and distinguished between operations","Because all chips use the same network topology"],"answer":1,"explanation":"The receiver and the path are part of a physical implementation of a computation."},"science":[{"title":"A communication edge","equation":"t_{edge} = α + M/\\beta,\\qquad E_{edge}=M e_{bit}","explanation":"A simple edge model separates startup latency α from payload transfer M/β and scales energy with transferred bits and an effective energy-per-bit term.","assumptions":"Homogeneous effective bandwidth and energy; protocol overhead, contention and topology require additional terms."}],"history":[],"prerequisites":["crg-problem-statement","on-chip-network"],"learningObjective":"Draw a communication edge with a payload, receiver, timing boundary and error condition.","workstream":"CRG","visualFamily":"signal-power","engineeringExample":"For a 1 GB collective payload over a 100 GB/s effective path with 5 μs startup, the payload term is about 10 ms; a topology or contention change can dominate the same arithmetic operation.","evidenceNotes":"The edge equation is a bounded teaching model. Shannon’s source addresses communication limits; it does not by itself specify a chip architecture.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}