The mechanism
The canonical six-transistor SRAM cell contains two cross-coupled inverters plus two access transistors. The inverter pair reinforces one of two stable states while power remains applied. A word line enables access to complementary bit lines for reading or writing. Read and write circuitry around the array is essential: a lone cell does not provide a complete addressable memory. The atlas lets viewers inspect one feedback loop and then see it repeated in rows and columns with shared access wiring. This explains both the compactness of an array and the nonzero cost of moving data into and out of it. Static means no periodic refresh requirement, not permanent retention without power.
- Use two cross-coupled inverters to reinforce one stable stored state.
- Enable access transistors with the selected word line.
- Read or change the state through bit lines and the array’s peripheral circuits.
Science and assumptions
Feedback equilibria
At equilibrium, each storage-node voltage equals its inverter response to the other node voltage.
Symbols and units
- x
- First storage-node voltage
V
- y
- Second storage-node voltage
V
- f
- First inverter static voltage-transfer function
V → V
- g
- Second inverter static voltage-transfer function
V → V
Two inverter transfer functions constrain both storage-node voltages simultaneously. The useful states are stable equilibria; a central metastable equilibrium separates them.
Assumptions Static two-inverter teaching model with powered feedback; read/write access, noise margins, mismatch, and transient stability need circuit analysis.
Engineering example
Synthetic 1 KiB payload contains 1,024 × 8 = 8,192 bits. At six transistors per canonical cell, the cell array contains 49,152 transistors before decoders, sense amplifiers, write drivers, redundancy and control are added.
Distinctions and tradeoffs
Static RAM is volatile: static refers to retention without periodic refresh while powered, not retention after power loss.
Dense cells save area. Read stability, write ability, and leakage constrain sizing and voltage.
On-chip SRAM keeps working data near arithmetic units. Local reuse reduces repeated traffic to more distant memory.
Specifications and interfaces
- Canonical bit cell
- 6 transistors
Four latch devices plus two access devices.
- Retention
- While powered
SRAM is volatile.
- Array wiring
- Word line + bit lines
Decoders and sensing circuits are outside the cell.
Interfaces
- Word line and bit lines Input
- Read/write selection and data
- Stored bit Output
- Local state accessed through array circuitry
Check your understanding
What does the canonical 6T cell need to retain data?
- A permanent magnetic field
- An optical laser refreshing every row
- Continued electrical power
Answer and reasoning
Continued electrical power
The stored state is maintained by powered feedback. Removing power loses the guarantee of retained data.
Evidence and scope
The six-transistor topology follows the linked SRAM lecture. The arithmetic is an ideal payload count, not a physical macro area, transistor total or proof of read/write stability.
Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.