{"id":"wafer-finishing-geometry","level":"matter","name":"Wafer finishing, orientation and geometry","shortName":"Wafer finishing, orientation and geometry","role":"Turns an ingot slice into a clean, geometrically controlled starting surface.","description":"A sliced wafer carries machining damage and geometry that later tools must tolerate. Lapping or grinding controls thickness and parallelism; chemical removal addresses damaged material; polishing prepares the surface. Crystal orientation describes the lattice relative to that surface, while a notch supplies an alignment reference. Thickness variation, bow and warp describe different departures from an ideal disk. A wafer can be smooth locally yet bend across its diameter, affecting focus or chuck contact. This lesson follows the same wafer from slicing to inspection and keeps surface roughness, global shape, usable area and crystal orientation as separate engineering quantities.","specs":[{"label":"Thickness variation","value":"TTV = maximum − minimum thickness","context":"Both measurements use the same wafer and thickness map; length units must match."},{"label":"Usable boundary","value":"Edge exclusion","context":"A product/tool-specific unusable rim, not a universal wafer constant."}],"interfaces":[{"name":"Crystal ingot","direction":"in","signal":"Oriented bulk material with traceable identity"},{"name":"Polished wafer","direction":"out","signal":"Clean face, controlled thickness map and orientation reference"}],"tradeoff":"Removing more material can reduce machining damage but consumes thickness and adds processing cost.","whyAI":"Flat, consistently supported wafers help focus, bonding and thin-film uniformity across the many dies sharing one process history.","related":["silicon-wafer","electronic-silicon-crystal-growth","temporary-carrier-thinning"],"sources":[{"title":"SUMCO — Production Processes","url":"https://www.sumcosi.com/english/products/process/"},{"title":"DISCO — Tech Briefing 2023","url":"https://disco.co.jp/jp/ir/movie/doc/E_Tech_Briefing_2023.pdf"}],"scale":"Atomic lattice to full wafer; geometry schematic","kind":"process","branch":"Fabrication / Materials","subbranch":"From crystal to starting wafer","mechanism":["Slice the ingot and retain its orientation and genealogy in the wafer identifier.","Reduce thickness variation while controlling the two wafer faces rather than only their average spacing.","Remove damaged surface material left by mechanical machining.","Polish and clean the wafer without treating mirror appearance as proof of atomic cleanliness.","Measure thickness, shape and surface defects; relate each measurement to the next tool interface."],"misconception":"Low surface roughness does not imply low bow, low warp or low total thickness variation.","check":{"question":"Which observation best explains a wafer that is smooth but has inconsistent focus across its diameter?","options":["Crystal orientation has become a different element","A global shape or chucking issue may remain","Mirror finish guarantees constant focus"],"answer":1,"explanation":"Local texture and whole-wafer shape occupy different spatial scales and require different measurements."},"science":[{"title":"Usable circular area","equation":"Aᵤ = π(R − e)²","explanation":"R is wafer radius and e edge exclusion in the same length unit; Aᵤ is the remaining circular area.","assumptions":"This is area only, not gross die count. Rectangular die packing, scribe streets and partial edge dies still matter."}],"prerequisites":["silicon-wafer"],"learningObjective":"Explain how wafer surface quality differs from global wafer geometry.","workstream":"W01","visualFamily":"process-wafer","engineeringExample":"Synthetic geometry: a 150 mm radius disk with a 3 mm excluded rim has about 67,887 mm² of usable circular area. Dividing this by die area still overestimates complete rectangular dies near the edge.","evidenceNotes":"Illustrative geometry does not establish a production edge exclusion or thickness specification.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}