{"id":"standard-cell","level":"logic","name":"Standard-cell library and physical design","shortName":"Standard cells","role":"Packages characterized transistor circuits into reusable building blocks for chip layout.","description":"A standard-cell library gives designers reusable implementations of logic and sequential functions. A cell is more than its Boolean symbol: it also has physical geometry, pin locations, timing behavior, and electrical loading. Design tools select cells to implement a circuit, place them within allowed regions, and route their connections under process rules. Multiple drive strengths and variants let the implementation trade area, speed, and power. The atlas shows rows of distinct cells underneath the routing layers, making the transition from a circuit graph to a physical layout visible. Large memories and specialized datapaths may use dedicated macros or custom design, so the entire chip is not necessarily a uniform sea of identical standard cells.","specs":[{"label":"Library views","value":"Function, timing, physical geometry","context":"Different abstractions describe the same cell."},{"label":"Implementation flow","value":"Synthesis → placement → routing","context":"Verification checks the resulting design."},{"label":"Cell examples","value":"Inverter, NAND, D flip-flop","context":"Typical reusable library functions."}],"interfaces":[{"name":"Logic specification and process rules","direction":"in","signal":"Required function and legal implementation constraints"},{"name":"Placed and routed circuit","direction":"out","signal":"Manufacturable physical realization"}],"tradeoff":"Reuse speeds implementation and characterization. Custom blocks can improve selected functions at greater design cost.","whyAI":"Standard cells turn large AI chip designs into buildable circuits. Physical design makes their abstract connectivity fit real area and timing constraints.","related":["inverter","nand","flipflop","sram","interconnect","finfet","gaa"],"sources":[{"title":"University of Texas — Standard Cell Library","url":"https://www.cerc.utexas.edu/~jaa/projects/library/"},{"title":"University of Southampton — Digital CMOS Standard-Cell Design","url":"https://www.southampton.ac.uk/~bim/notes/icd/lecture/pdf4/icd07.pdf"}],"scale":"Microscopic cells placed across a millimeter-scale die","kind":"standard-cell","mechanism":["Map required logic into characterized cell functions and variants.","Place those cells where the geometry, power, and timing constraints permit.","Route and verify their connections to produce a physical circuit consistent with the intended function."],"misconception":"A logic symbol alone is not enough to manufacture a cell; physical, electrical, timing, and process-rule information are also needed.","check":{"question":"Which information belongs to a useful standard-cell library?","options":["Only the name of the software model","Only a color for each cell","Function, timing, loading, geometry, and connection information"],"answer":2,"explanation":"Implementation tools need both logical behavior and physical/electrical constraints to assemble a functioning chip."},"branch":"Physical design","subbranch":"Cell placement","science":[{"title":"Placement utilization","equation":"U = Σ A_cell / A_placeable","explanation":"Higher utilization packs more cell area into the available region. Remaining space is useful for routing access, buffers, clock distribution, and legal placement constraints.","assumptions":"Area bookkeeping metric; no single utilization target is optimal across process nodes or block types."}],"history":[],"learningObjective":"Relate library choice to area utilization and wiring.","engineeringExample":"A design with high cell-area utilization can still lose frequency to congestion, buffering and long routes; U is one floorplanning metric.","evidenceNotes":"The ratio excludes macro placement, whitespace policy and timing closure.","visualFamily":"design-flow","prerequisites":["nand","clock"],"labId":"library","scope":"Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.","investigationId":"switching","labScope":"Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism."}