{"id":"soic-foveros-vertical-routes","level":"package","name":"SoIC and Foveros: vertical integration families","shortName":"SoIC and Foveros: vertical integration families","role":"Compares named die-stacking routes while preserving their base-die and bonding differences.","description":"Vertical integration places functional dies above other silicon, shortening selected connections and changing the thermal and test problem. TSMC SoIC-X describes dense chip-on-wafer and wafer-on-wafer stacking routes. Intel’s Foveros family spans distinct implementations; its cited brief distinguishes passive-base integration from Foveros Direct 3D with hybrid bonding to an active base. These are technology families, not one universal stack recipe. A vertical assembly can also become an input to a larger package containing lateral links and HBM. The viewer follows the chosen route’s base, upper die and interfaces, and compares thermal access and tested-die selection alongside connection density.","specs":[{"label":"Route identity","value":"Die-to-wafer vs wafer-to-wafer","context":"Different matching, selection and handling opportunities."},{"label":"Base function","value":"Passive routing or active circuitry","context":"Must be specified for the selected implementation, not inferred from its position."}],"interfaces":[{"name":"Prepared die or wafer pair","direction":"in","signal":"Matched interfaces, test status and compatible material stacks"},{"name":"Vertical assembly","direction":"out","signal":"Short inter-die connections plus new power/thermal/test constraints"}],"tradeoff":"Denser vertical connections can reduce communication distance while making heat removal, test access and defect propagation more difficult.","whyAI":"Logic/cache or logic/logic partitioning can place useful resources closer, but useful workload benefit depends on the complete memory and thermal design.","related":["hybrid-bond-surface-alignment","temporary-carrier-thinning","cowos-s-silicon-interposer","backside-power-dtco"],"sources":[{"title":"TSMC — SoIC","url":"https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm"},{"title":"Intel Foundry — Accelerating HPC and AI","url":"https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf"},{"title":"Intel — New Architectures and Technologies Target Expanded Market Opportunities","url":"https://www.intc.com/news-events/press-releases/detail/106/new-intel-architectures-and-technologies-target-expanded"}],"scale":"Multi-die package to selected joint; not dimensionally identical alternatives","kind":"integration","branch":"Packaging / Interposers, bridges and stacking","subbranch":"Alternative integration routes","mechanism":["Select a named family variant and specify whether the base contains active circuits or passive routing.","For die-to-wafer, select screened dies and place them onto a receiving wafer; for wafer-to-wafer, match whole wafer arrays.","Prepare and join interfaces using the bonding technology disclosed for that route.","Complete thinning, vertical access and testing operations appropriate to the stack.","Integrate the vertical assembly into its larger package while checking thermal and power paths."],"misconception":"All Foveros generations are not identical, and a vertical stack does not automatically imply a particular hybrid-bond pitch.","check":{"question":"What changes when moving from whole-wafer bonding to die-to-wafer placement?","options":["Individual die selection becomes possible, with added placement/handling demands","Every thermal issue disappears","No receiving interface is needed"],"answer":0,"explanation":"The matching unit changes from a full wafer pair to selected dies and their receiving sites."},"science":[{"title":"Unscreened pair yield","equation":"Y_pair = P(top good ∩ bottom good) ≈ Y_top Y_bottom","explanation":"Y values are probabilities over matched die sites before bonding.","assumptions":"Product form requires independence and no screening. Screened die-to-wafer flows need conditional incoming quality plus new assembly losses."}],"prerequisites":["known-good-die-test","cowos-s-silicon-interposer"],"learningObjective":"Distinguish vertical route selection, base-die function and bonding technology.","workstream":"W05","visualFamily":"package-route","engineeringExample":"Synthetic wafer pair: two independent 90% die-yield wafers have about 81% coincident good sites before bonding losses. Applying 81% to individually screened dies would incorrectly reuse raw wafer losses.","evidenceNotes":"Branded technologies evolve. The animation must identify the cited variant, and no complete proprietary flow or current product qualification is claimed.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}