{"id":"simt-active-lanes","level":"compute","name":"SIMT execution and divergent branches","shortName":"SIMT execution and divergent branches","role":"Shares instruction issue across threads while tracking which lanes participate.","description":"A GPU kernel describes many threads, but execution resources issue instructions to groups of threads. Threads can have different addresses and control decisions; the machine uses active masks to determine which lanes participate in a particular instruction. When a group takes different branches, the paths may require separate masked execution. Coalescing is a different concern: neighboring addresses can be combined into efficient memory transactions even when the arithmetic is identical. NVIDIA warps and AMD wavefronts instantiate related ideas with generation-specific details. The useful comparison follows the same small operation through these groups, counting both idle lanes and transferred bytes.","specs":[{"label":"Active-lane fraction","value":"Useful participating lanes / group width","context":"A dimensionless instruction-level metric, distinct from chip utilization."},{"label":"Transaction efficiency","value":"Requested bytes / transferred bytes","context":"Depends on address alignment, access size and memory behavior."}],"interfaces":[{"name":"Kernel threads","direction":"in","signal":"Per-thread values, predicates and addresses"},{"name":"Execution group","direction":"out","signal":"Masked instructions and memory transactions"}],"tradeoff":"Grouping similar requests can reduce divergence and scattered accesses, but rearranging them costs time and can increase request latency.","whyAI":"Irregular token lengths, sparse experts and gathers can leave SIMD-style resources underused even when a model has a large total operation count.","related":["streaming-multiprocessor","kernel","gpu-occupancy-pipeline"],"sources":[{"title":"CUDA C++ Programming Guide","url":"https://docs.nvidia.com/cuda/cuda-c-programming-guide/"},{"title":"AMD Instinct MI300 Series microarchitecture","url":"https://rocm.docs.amd.com/en/latest/reference/gpu-arch/mi300.html"}],"scale":"GPU execution group to package; schematic topology","kind":"architecture","branch":"Processing architectures","subbranch":"GPU execution and placement","mechanism":["Assign logical threads to an execution group under the target architecture’s documented rules.","Issue a common operation for the lanes whose predicates are active at that point.","If control flow splits, execute the required paths with masks and reconverge according to the program.","Translate each participating lane’s address into memory transactions; contiguous addresses usually waste fewer transferred bytes.","Compare useful outputs, active masks and actual transactions before attributing low performance to insufficient arithmetic units."],"misconception":"Divergence and uncoalesced memory access are separate effects; either can occur without the other.","check":{"question":"All threads run the same instruction but read widely separated addresses. What is the likely issue?","options":["Memory transaction inefficiency","Necessarily branch divergence","Mandatory out-of-order retirement"],"answer":0,"explanation":"Uniform control can still generate many memory transactions when the addresses do not fall into shared transaction regions."},"science":[{"title":"Masked execution efficiency","equation":"u = Σ active_lanes / Σ issued_lane_slots","explanation":"Count lane participation over issued instructions. The resulting fraction measures mask waste and has no time units.","assumptions":"Equal-cost instructions in this toy metric; real latency and throughput differ across instructions."}],"prerequisites":["kernel","streaming-multiprocessor"],"learningObjective":"Distinguish divergent control from inefficient address coalescing.","workstream":"W07","visualFamily":"architecture-gpu","engineeringExample":"Synthetic eight-lane group: four lanes require one ten-instruction branch and four require a different ten-instruction branch. If both paths execute under masks, 80 useful lane-instructions occupy 160 issued slots.","evidenceNotes":"The eight-lane drawing is pedagogical, not a claimed NVIDIA or AMD execution-group width. Cross-vendor scheduling details are intentionally not equated.","labId":"library","scope":"Use the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.","investigationId":"execution","labScope":"Use the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism."}