{"id":"silicon-wafer","level":"matter","name":"Wafer and fabrication hierarchy","shortName":"Silicon wafer","role":"Provides the shared substrate on which many integrated circuits are fabricated.","description":"A wafer is a thin, polished slice of highly purified crystalline silicon. Many die patterns are processed across its surface together before testing and singulation separate usable chips. Device formation near the surface is commonly described as front end of line, or FEOL; local connections bridge devices to the back end of line, or BEOL, wiring stack. These labels describe manufacturing regions, not software front ends and back ends. Repeated patterning, deposition, removal, cleaning, and measurement build the structures layer by layer. The atlas compresses this long chain into a navigable cross section so viewers can connect a macroscopic wafer to the tiny electrical structures it carries.","specs":[{"label":"Example wafer diameter","value":"300 mm","context":"Widely used advanced-logic manufacturing format; not universal."},{"label":"Thickness","value":"Less than 1 mm","context":"General introductory wafer description, not a procurement specification."},{"label":"Hierarchy","value":"Wafer → die → package","context":"Test and assembly intervene between stages."}],"interfaces":[{"name":"Purified crystal","direction":"in","signal":"Mechanically supported semiconductor substrate"},{"name":"Fabricated dies","direction":"out","signal":"Patterned and tested integrated circuits"}],"tradeoff":"Larger useful die area can reduce unit cost. Defects, edge loss, and yield complicate that benefit.","whyAI":"AI accelerators emerge from this manufacturing platform. Wafer yield and die size influence the cost of available compute.","related":["crystal-lattice","lithography","cmp","mosfet","interconnect"],"sources":[{"title":"Intel — Semiconductors and Intel: An Introduction","url":"https://www.intel.com/content/dam/www/central-libraries/us/en/documents/semiconductors-and-intel-introduction.pdf"},{"title":"Electronic Materials and Fabrication — Productivity and Process Yield","url":"https://staff-old.najah.edu/sites/default/files/Lec29.pdf"}],"scale":"300 mm example wafer carrying microscopic structures","kind":"wafer","mechanism":["Begin with a polished crystalline wafer that supports many die locations.","Build device regions and wiring through repeated patterning and material-processing stages.","Test the fabricated structures, separate die, and assemble usable die into packages."],"misconception":"A wafer, a die, and a package are different objects; one patterned wafer normally contains many die.","check":{"question":"Which order follows physical integration?","options":["Package → atom → wafer","Wafer → fabricated die → package","Metal gate → data center → dopant"],"answer":1,"explanation":"Die are fabricated across a wafer and later separated for assembly. Testing and yield determine which proceed."},"branch":"Fabrication","subbranch":"Wafer and yield","science":[{"title":"A first defect-yield model","equation":"Y ≈ exp(−D₀ A_die)","explanation":"If random fatal defects occur at density D₀ per unit area, larger die area increases the chance of encountering one. Yield affects how many functional chips emerge from the same wafer.","assumptions":"Illustrative Poisson model with independent uniform fatal defects; real yield uses process-specific models, clustering, repair, and many nonrandom factors."}],"history":[],"learningObjective":"Separate wafer area, die geometry, starts and good output.","engineeringExample":"A 300 mm wafer with edge exclusion can contain thousands of nominal sites, but the good-die count falls with die area and defect exposure.","evidenceNotes":"Gross-site geometry and yield are teaching estimates; reticle fields, scribe lanes and parametric loss are not hidden.","visualFamily":"process-wafer","prerequisites":["crystal-lattice"],"labId":"engineering","scope":"Explore gross sites and random-defect survival; geometric approximations and defect models do not replace wafer test.","deepLabId":"wafer","investigationId":"manufacturing","labScope":"Explore gross sites and random-defect survival; geometric approximations and defect models do not replace wafer test."}