{"id":"register-file","level":"die","name":"Register file","shortName":"Registers","role":"Keeps each active thread’s immediate values close to the arithmetic pipelines.","description":"Registers hold the addresses, counters, partial results, and scalar operands that threads need immediately. The compiler assigns program values to a finite physical pool. A value in a register does not need a fresh trip to off-chip memory for every instruction. If a kernel asks for too many registers, fewer blocks may fit at once; some values may also spill into local memory, which is backed by device memory and cached. Registers are private to a thread in the programming model, although explicit warp shuffle instructions can exchange values between participating threads. Local register reuse keeps operands near arithmetic lanes; a spill adds memory traffic and can lengthen the path to the same result.","specs":[{"label":"Pool per SM","value":"64K × 32-bit registers","context":"Blackwell architectural register-file count."},{"label":"Per-thread limit","value":"255 registers","context":"Architectural maximum; allocation granularity and occupancy also matter."},{"label":"Warp exchange","value":"Shuffle instructions","context":"Explicit register-value exchange among participating warp threads."}],"interfaces":[{"name":"Load or computation","direction":"in","signal":"Thread-local values"},{"name":"Execution operands","direction":"out","signal":"Addresses and arithmetic inputs"},{"name":"Spill path","direction":"out","signal":"Values moved to device-backed local memory"}],"tradeoff":"Keeping more intermediates in registers can reduce traffic, but large allocations limit parallel residency. Kernel fusion therefore needs a balance between reuse and register pressure.","whyAI":"Matrix kernels, normalization, and attention all reuse small values many times. Register allocation can change their speed even when the mathematical model remains identical.","related":["streaming-multiprocessor","tensor-core","l1-cache","sram","kernel"],"sources":[{"title":"NVIDIA CUDA Blackwell Tuning Guide","url":"https://docs.nvidia.com/cuda/blackwell-tuning-guide/index.html"},{"title":"NVIDIA: Register Cache for Warp-Centric CUDA Programs","url":"https://developer.nvidia.com/blog/register-cache-warp-cuda/"}],"scale":"On-die storage banks; physical bank dimensions are schematic","kind":"register-banks","mechanism":["The compiler maps frequently used thread values to registers, subject to the available register pool and allocation rules.","Execution pipelines repeatedly read and update those nearby values without fetching them anew from HBM.","If register demands exceed a useful allocation, parallel residency can fall or values can spill to device-backed local memory."],"misconception":"CUDA local memory does not mean physically nearest to a thread. Register spills to local memory are backed by device memory and may be cached.","check":{"question":"What can happen when each thread uses many more registers?","options":["The GPU gains more physical register capacity automatically.","The model becomes permanently stored on the die.","Fewer blocks fit concurrently, or some values spill."],"answer":2,"explanation":"Registers are a finite resource shared among resident work. More per-thread state can trade local reuse for lower concurrency or extra memory traffic."},"branch":"Memory hierarchy","subbranch":"On-chip storage","science":[{"title":"Register allocation limits resident work","equation":"Bresident ≤ floor(RSM / (rthread × Tblock))","explanation":"RSM is the number of available 32-bit registers per SM, rthread is registers requested per thread, and Tblock is threads per block. Their product estimates the register footprint of one block. Doubling the per-thread requirement can reduce the number of blocks that fit, even though it may save loads by retaining more intermediate results.","assumptions":"A register-only upper bound, assuming uniform allocation. Hardware allocation granularity, reserved resources, warp/block limits, and shared-memory use can lower residency further. It is not a complete CUDA occupancy calculator."}],"history":[],"learningObjective":"Explain why registers can limit occupancy.","engineeringExample":"If each thread consumes more registers, floor(R_SM/(r_thread T_block)) decreases even if arithmetic units remain available.","evidenceNotes":"The model ignores allocation granularity, spilling and architecture-specific limits.","visualFamily":"memory-route","prerequisites":["flipflop","sram"],"labId":"library","scope":"Use the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.","investigationId":"execution","labScope":"Use the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism."}