{"id":"pcie-cxl-semantics","level":"infrastructure","name":"PCIe and CXL: transport versus memory semantics","shortName":"PCIe and CXL","role":"Distinguishes peripheral data transfer from supported coherent memory operations.","description":"PCI Express provides a widely used physical and protocol foundation for host devices. CXL builds on a PCIe physical foundation while adding defined cache and memory semantics alongside I/O. This enables supported devices to participate in coherent access or expose memory through specific host/device roles. It does not make distant memory equivalent to local DRAM: requests still cross links, queues and controllers. Software, firmware and device generation determine what is actually enabled. Both the physical route and the ownership or coherence behavior matter: equal link rates do not imply identical programming semantics.","specs":[{"label":"Protocol roles","value":"CXL.io, CXL.cache and CXL.mem","context":"Supported roles depend on device type and version."},{"label":"Memory expansion","value":"Additional addressable capacity","context":"Capacity does not guarantee local-memory latency or bandwidth."}],"interfaces":[{"name":"Host requests","direction":"in","signal":"I/O transactions or supported coherent memory operations"},{"name":"Device or attached memory","direction":"out","signal":"Completions, data and coherence responses"}],"tradeoff":"Expanded or shared memory can improve capacity utilization while exposing link latency and management complexity.","whyAI":"Model state that does not fit near an accelerator may use a larger memory tier, but traffic-sensitive operations need a measured access budget.","related":["pcie-interface","ddr-memory","die-link-compatibility"],"sources":[{"title":"Compute Express Link 2.0 Specification Now Available","url":"https://computeexpresslink.org/blog/compute-express-link-2-0-specification-now-available-2374/"}],"scale":"Micrometers of package wiring to board-scale links; schematic","kind":"architecture","branch":"Chip-to-hall integration","subbranch":"Interface compatibility and electrical budgets","mechanism":["Identify host and device roles and the CXL version supported by both endpoints.","Separate ordinary I/O transactions from enabled cache or memory protocol operations.","Map memory ownership and address translation consistently across the system.","Trace requests through physical links and controllers despite a convenient software address model.","Measure the intended workload before treating expanded memory as a substitute for nearby capacity."],"misconception":"Coherence supplies consistency rules; it does not erase physical distance or guarantee identical access cost.","check":{"question":"What does adding CXL memory establish most directly?","options":["Automatic HBM bandwidth for every request","An enabled additional memory resource with defined access semantics","The same latency as every CPU cache"],"answer":1,"explanation":"Actual access time and rate remain properties of the complete implemented path."},"science":[{"title":"Two-tier access estimate","equation":"Lavg = pLnear + (1−p)Lfar","explanation":"p is the near-access fraction and latency values are seconds/access.","assumptions":"Simple average without overlap or queueing; a dependent chain or tail metric needs additional analysis."}],"prerequisites":["pcie-interface","ddr-memory"],"learningObjective":"Explain why physical transport, coherent semantics and memory performance are distinct.","workstream":"W09","visualFamily":"signal-power","engineeringExample":"Synthetic placement: moving a rarely accessed 10 GB table to a larger tier may free nearby memory for hot state. Moving a repeatedly streamed hot tensor can instead increase runtime despite identical total capacity.","evidenceNotes":"CXL 2.0 is a historical teaching disclosure. No latest-generation support, universal latency or arbitrary platform compatibility is asserted.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}