{"id":"on-chip-network","level":"die","name":"On-chip interconnect fabric","shortName":"On-chip fabric","role":"Routes data and control between compute units, cache slices, memory controllers, and I/O.","description":"The on-chip fabric is the communication system within the silicon. Requests carry addresses, operation types, and data between blocks; arbitration decides which request uses a contested path. Wires have capacitance and resistance, so longer journeys consume time and energy even before leaving the package. A GPU can expose a unified address space while still having internal locality domains. An illustrative routing graph is distinct from an undisclosed physical topology: a tidy mesh is a teaching model, not evidence that Blackwell uses that exact network. Shared routes can create contention, and local versus remote cache access can use different paths; the chip’s communication behavior matters alongside its arithmetic.","specs":[{"label":"Endpoints","value":"SMs, cache, memory, I/O","context":"Logical component classes; exact proprietary topology is not asserted."},{"label":"Address view","value":"Unified GPU memory space","context":"Physical locality can still affect movement cost."},{"label":"Constraint","value":"Bandwidth, latency, and energy","context":"No unsupported numerical internal-fabric rating is assigned."}],"interfaces":[{"name":"Request injection","direction":"in","signal":"Addressed transactions from compute or I/O"},{"name":"Routing","direction":"out","signal":"Packets or transactions to selected internal endpoints"},{"name":"Backpressure","direction":"in","signal":"Flow-control information from occupied resources"}],"tradeoff":"Wider routes and more buffering improve communication capacity but consume area and power. Placing related work and data near one another can reduce movement before any hardware is added.","whyAI":"Thousands of concurrent tensor operations must obtain operands and exchange results. Internal communication determines whether the advertised arithmetic units remain busy.","related":["streaming-multiprocessor","l2-cache","hbm-controller","nvlink-port","gpu-die","interconnect"],"sources":[{"title":"NVIDIA: GPU locality domains and L2 fabric","url":"https://developer.nvidia.com/blog/accelerating-data-processing-with-nvidia-multi-instance-gpu-and-numa-node-localization/"},{"title":"Intel: Memory performance, latency, and bandwidth","url":"https://www.intel.com/content/www/us/en/developer/articles/technical/memory-performance-in-a-nutshell.html"},{"title":"John D. C. Little (1961): A Proof for the Queuing Formula L = λW","url":"https://pubsonline.informs.org/doi/abs/10.1287/opre.9.3.383"}],"scale":"Millimeter-to-centimeter internal routes; illustrative topology","kind":"transaction-routing-network","mechanism":["A compute, cache, or I/O block injects an addressed transaction into the chip’s communication fabric.","Routing and arbitration carry that transaction toward its destination while managing competition and backpressure.","The response returns through the fabric; repeated or long-distance traffic consumes bandwidth, energy, and time."],"misconception":"The atlas’s routing graph is a teaching diagram, not a verified Blackwell mesh layout. A physical topology should not be inferred from the illustrative geometry.","check":{"question":"Why does locality still matter inside one GPU?","options":["Only data outside the rack require energy to move.","Internal wires and shared routes still incur delay, energy, and contention.","One GPU contains only one possible data route."],"answer":1,"explanation":"Even on one chip, communication has physical costs. Keeping related data and work nearby can reduce unnecessary traffic."},"branch":"Connectivity","subbranch":"On-chip communication","science":[{"title":"Enough requests must be in flight","equation":"Ninflight = λ × L; Minflight ≈ B × L","explanation":"Little’s law relates average in-flight request count N to completed requests per second λ and average request latency L. Multiplying byte throughput B by latency gives the corresponding amount of in-flight data. A fabric can have wide links yet remain underused if the workload or queues cannot sustain enough independent transactions to cover the round trip.","assumptions":"Stable steady-state averages with the same system boundary for arrivals, completions, and latency. The byte form assumes consistent payload accounting. It supplies a concurrency requirement, not a claim about Blackwell’s undisclosed queue depths."}],"history":[],"learningObjective":"Relate in-flight data to rate and latency.","engineeringExample":"At 2 TB/s and 100 ns of round-trip latency, the bandwidth-delay product is 200 kB of in-flight data before protocol overhead.","evidenceNotes":"The relation assumes a stable stream and excludes topology-specific backpressure.","visualFamily":"signal-power","prerequisites":["interconnect","l2-cache"],"labId":"library","scope":"Use the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.","investigationId":"execution","labScope":"Use the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism."}