{"id":"nvme-storage","level":"server","name":"NVMe solid-state storage","shortName":"NVMe SSD","role":"Persists datasets, model checkpoints, and software beyond power cycles.","description":"An NVMe SSD combines nonvolatile NAND flash, a controller, firmware, and a fast host interface. It stores data persistently rather than providing the byte-addressable working memory used directly by arithmetic units. The controller maps logical blocks to flash locations, handles error management, and schedules reads and writes across internal parallelism. Large sequential transfers and small random accesses stress different parts of the device, so one speed number cannot describe every workload. Loading a checkpoint moves persistent data into working memory; repeated tensor computation then uses that working state, with different access and lifetime requirements. Supported direct-storage paths can reduce extra copies, but the storage device still has its own latency, bandwidth, and endurance limits.","specs":[{"label":"Micron 9550 example","value":"Up to 14.0 GB/s sequential read","context":"Vendor-rated maximum; capacity, host, and test conditions matter."},{"label":"Sequential write","value":"Up to 10.0 GB/s","context":"Micron 9550 selected configurations; not all capacities reach this."},{"label":"Host protocol","value":"NVMe over PCIe Gen5","context":"The protocol and physical interface are distinct layers."}],"interfaces":[{"name":"Read/write commands","direction":"in","signal":"Logical block requests"},{"name":"Persistent data","direction":"out","signal":"Dataset batches, model files, and checkpoints"},{"name":"Checkpoint writes","direction":"in","signal":"Training state committed for recovery"}],"tradeoff":"Storage offers durable capacity but is far slower than on-chip memory and HBM. Checkpoint frequency trades recovery effort against write traffic and interruption to useful work.","whyAI":"Training begins with stored data and produces checkpoints that must survive failures. Serving systems also need to load and update model artifacts reliably.","related":["pcie-interface","host-cpu","compute-baseboard","hbm-stack"],"sources":[{"title":"Micron 9550 NVMe data center SSD","url":"https://www.micron.com/products/storage/ssd/data-center-ssd/9550-ssd"},{"title":"Micron 9550 SSD technical product specification","url":"https://www.micron.com/content/dam/micron/global/public/products/data-sheet/ssd/9550-nvme-ssd-tech-prod-spec.pdf"},{"title":"John D. C. Little (2011): Little’s Law and computer architecture applications","url":"https://pubsonline.informs.org/doi/pdf/10.1287/opre.1110.0940"}],"scale":"Centimeter-scale module containing controller and NAND packages","kind":"checkpoint-storage-to-memory","mechanism":["The host issues block requests through the NVMe protocol to the SSD controller.","The controller maps those requests onto flash operations and uses internal parallelism and error handling to read or write data.","Data are loaded into working memory for computation, while completed checkpoints can be committed back to persistent storage."],"misconception":"NVMe storage capacity is not interchangeable with HBM capacity. Storage persists without power but has a different access model and much higher access cost.","check":{"question":"Why is a saved checkpoint useful after a node loses power?","options":["It remains in a powered-off GPU register.","It changes the physical number of Tensor Cores.","A nonvolatile storage copy survives when volatile working memory is lost."],"answer":2,"explanation":"Checkpoints persist the state needed for recovery. Their usefulness depends on what was saved and how recently it was committed."},"branch":"Host platform","subbranch":"Persistent storage","science":[{"title":"High IOPS requires enough outstanding work","equation":"QDaverage ≈ IOPS × Laverage","explanation":"Queue depth is the average number of operations in flight, IOPS is completed operations per second, and L is average latency in seconds. A drive capable of high throughput can remain underused if the application submits one request and waits before issuing the next. Increasing concurrency helps only until the storage, host link, or workload becomes the bottleneck.","assumptions":"Little’s law applied to a stable workload with a consistent measurement boundary. Latency generally changes with load, so the relation does not promise constant latency at arbitrary queue depth; read size, write mix, and durability requirements matter."}],"history":[],"prerequisites":["pcie-interface"],"learningObjective":"Use Little’s law to relate average outstanding I/O, throughput and latency within one storage boundary.","engineeringExample":"Synthetic stable workload: 100,000 IOPS at 200 μs average latency implies 100,000 × 0.0002 = 20 average outstanding operations. Doubling submitted queue depth does not imply double IOPS, because latency and the limiting resource may also change.","evidenceNotes":"This is a steady-state queueing identity applied to the storage boundary, as explained by the lesson. I/O size, read/write mix, persistence requirements and latency definition must match; no product performance is inferred.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}