{"id":"mask-opc-layout","level":"matter","name":"Masks, OPC and pattern-aware design","shortName":"Masks, OPC and pattern-aware design","role":"Pre-distorts a mask so the process prints a desired wafer pattern.","description":"A chip layout is not copied perfectly onto a wafer. Diffraction, neighboring shapes, resist response and etch transfer can move printed edges. Optical proximity correction modifies mask geometry to compensate for a calibrated imaging process. Some mask features assist printing without becoming intended device structures themselves. Mask manufacture and inspection introduce their own constraints, while multi-patterning can distribute one design across several exposures or spacer operations. The engineer therefore evaluates whether a design prints across a process window, not just at one ideal setting. This connects layout decisions and mask complexity directly to manufacturing yield.","specs":[{"label":"Design object","value":"Target wafer geometry vs mask geometry","context":"These are different coordinate/material objects."},{"label":"Error metric","value":"Edge placement error, length units","context":"Specify target edge, process stage and measurement convention."}],"interfaces":[{"name":"Layout and calibrated model","direction":"in","signal":"Target features, process assumptions and design rules"},{"name":"Manufacturable mask set","direction":"out","signal":"Corrected patterns with inspection and data-preparation requirements"}],"tradeoff":"More detailed correction may expand the usable process window while increasing computation, mask complexity and verification effort.","whyAI":"Accelerator layouts are valuable only if their dense patterns can be reliably fabricated and connected across many repeated layers.","related":["resist-track-development","lithography-resolution-focus","fab-metrology-process-window"],"sources":[{"title":"ASML — How microchips are made","url":"https://www.asml.com/en/technology/all-about-microchips/how-microchips-are-made"},{"title":"KLA — Practical Applications of Measurement System Analysis","url":"https://www.kla.com/documents/5.3_Practical_Applications_of_MSA_Sutherland_KLA.pdf"},{"title":"Applied Materials — New Ways to Shrink","url":"https://ir.appliedmaterials.com/static-files/f2fbf48d-a761-4c4f-ab4c-73f312ab1ebc"}],"scale":"Optical field to nanometer pattern; material states distinguished","kind":"process","branch":"Fabrication / Repeated operations","subbranch":"From resist image to etched feature","mechanism":["Define the wafer target and distinguish it from the starting drawn mask geometry.","Calibrate an imaging model using relevant patterns and process conditions.","Modify mask edges or assist features to reduce predicted wafer-edge error.","Verify neighboring pattern contexts and off-nominal conditions rather than a single nominal image.","Manufacture, inspect and qualify the mask before interpreting wafer defects as scanner-only problems."],"misconception":"OPC does not mean every extra shape on a mask is an extra transistor on the wafer.","check":{"question":"Why test a corrected mask across focus and exposure conditions?","options":["A good nominal image can still have a narrow process window","Focus and dose never affect resist geometry","The mask is the finished wafer"],"answer":0,"explanation":"Robust printing requires tolerating realistic variation, not merely matching the target at one calibrated point."},"science":[{"title":"Edge-error objective","equation":"E = Σᵢ wᵢ[eᵢ(predicted) − eᵢ(target)]²","explanation":"Edge coordinates e use length units; weights w state which edge/context matters. E has weighted length² units.","assumptions":"Illustrative optimization objective, not a proprietary OPC algorithm. Model error and manufacturing constraints require separate validation."}],"prerequisites":["lithography"],"learningObjective":"Explain why manufacturable mask geometry differs from desired wafer geometry.","workstream":"W02","visualFamily":"process-wafer","engineeringExample":"Illustrative pair: an isolated line and a dense line array share the same drawn width but print different widths. Context-dependent correction can address the mismatch; a uniform global width change may improve one and worsen the other.","evidenceNotes":"The mask schematic omits proprietary correction algorithms and exact design rules. No vendor node is equated with a single printable dimension.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}