{"id":"known-good-die-test","level":"die","name":"DFT, probe, binning and known-good die","shortName":"DFT, probe, binning and known-good die","role":"Uses designed test access and measurements to screen material before costly assembly.","description":"Testing needs access to behavior that ordinary product pins may not expose. Scan structures improve controllability and observability of logic; built-in self-test can exercise embedded memories; parametric structures measure electrical process behavior. Wafer probing then contacts designated pads to apply tests before singulation. Redundant memory resources may repair eligible faults, and binning classifies parts by defined function or performance. A known-good die has passed a stated screening flow; it is not guaranteed free of every latent defect. This matters especially when a package combines several valuable dies that can be lost together during subsequent integration.","specs":[{"label":"Test boundary","value":"Parametric, structural and functional tests","context":"Different tests cover different fault models and operating conditions."},{"label":"Output state","value":"Passed specified tests / repaired / binned","context":"Known-good status must include the test revision and conditions."}],"interfaces":[{"name":"Wafer and test access","direction":"in","signal":"DFT structures, probe pads and defined test program"},{"name":"Screened die map","direction":"out","signal":"Bin, repair status and genealogy for singulation and assembly"}],"tradeoff":"More test coverage can reduce expensive assembly escapes while adding test time, design overhead and possible over-screening.","whyAI":"Good-die selection protects packages containing compute, interposers and multiple memory stacks from avoidable incoming-part losses.","related":["flipflop","sram","wafer-handling-genealogy","hbm-stack-assembly-test"],"sources":[{"title":"Advantest — Semiconductor test glossary","url":"https://www.advantest.com/en/investors/ir-library/glossary/"},{"title":"Intel Foundry — Accelerating HPC and AI","url":"https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf"}],"scale":"Feature measurements, wafer maps and time-dependent production","kind":"process","branch":"Fabrication / Control, test and ramp","subbranch":"From processed wafers to released output","mechanism":["Build test access into the design so internal states can be controlled or observed.","Measure process parameters separately from structural and application-oriented functional behavior.","Probe dies under a defined program and retain failing-site and condition information.","Apply permitted redundancy and classify function/performance bins using explicit product criteria.","Preserve map identity through dicing and test again at later integration stages when new failure mechanisms appear."],"misconception":"Known-good die means passed a defined test set; it does not mean perfect detection of all current and future faults.","check":{"question":"Why is final package testing still needed after incoming dies passed wafer probe?","options":["Wafer probe has no useful information","Every tested die becomes electrically identical","Assembly can introduce new interconnect or mechanical failures"],"answer":2,"explanation":"Incoming screening and assembly verification examine different failure opportunities and interfaces."},"science":[{"title":"Screened defect probability","equation":"P(defect | pass) = p(1−c) / [1−pc]","explanation":"p is incoming defect probability and c detection probability for that defect population; all terms are dimensionless.","assumptions":"Assumes no false rejects and a single defined defect population. Real fault coverage and test sensitivity are not interchangeable without validation."}],"prerequisites":["yield-wafer-defect-model"],"learningObjective":"Explain what DFT, probe, repair and binning establish before package integration.","workstream":"W04","visualFamily":"fab-operations","engineeringExample":"Synthetic screening: p = 0.10 and c = 0.90 leave 0.01/0.91 ≈ 1.10% defective among passing parts under the simple assumptions. Applying the raw 10% defect rate again to screened parts would double-count the screen.","evidenceNotes":"No actual tester coverage or product escape rate is asserted. Dicing routes vary, and not all damage can be detected by the same test.","labId":"library","scope":"No current calculator directly models this lesson’s main mechanism. Use the library for related bounds while retaining their stated omissions.","investigationId":"manufacturing","labScope":"No current calculator directly models this lesson’s main mechanism. Use the library for related bounds while retaining their stated omissions."}