{"id":"interposer","level":"package","name":"Interposer and redistribution layers","shortName":"Interposer","role":"Connects logic dies and memory through dense package-level wiring.","description":"The interposer is the wiring platform between fine-pitch die connections and the larger package substrate. It lets a GPU sit close to several memory stacks with many parallel connections. Advanced packaging does not always use a single uniform slab of silicon: TSMC’s CoWoS family includes silicon interposers, redistribution-layer approaches, and local silicon interconnects embedded where higher connection density is needed. A GPU-to-HBM route passes through selected conductors and connections in the routing platform. A generic routing construction does not establish the exact unpublished package cross-section of a named accelerator. Dense local wiring makes the package function like a small system assembled from dies optimized for different jobs.","specs":[{"label":"Integration class","value":"2.5D heterogeneous packaging","context":"Logic and memory sit side by side on dense interconnect structures."},{"label":"CoWoS-L structure","value":"RDL plus local silicon interconnects","context":"TSMC platform description, not a specific Blackwell bill of materials."},{"label":"CoWoS-S example","value":"Up to about 2,700 mm² interposer","context":"TSMC stated 3.3-reticle platform capability; not a GPU die area."}],"interfaces":[{"name":"Die terminals","direction":"in","signal":"Fine-pitch signals from GPU and HBM"},{"name":"Lateral links","direction":"out","signal":"Dense routes between adjacent dies"},{"name":"Substrate escape","direction":"out","signal":"Signals and power paths toward the package substrate"}],"tradeoff":"Denser routing reduces connection distance but increases fabrication and assembly complexity. Different interposer styles balance routing density, mechanical behavior, package size, and cost.","whyAI":"The memory bandwidth of an accelerator depends on the wiring that joins logic and HBM. Advanced packaging enables system-level gains even when transistor scaling alone slows.","related":["gpu-die","hbm-stack","microbump","package-substrate","cmp"],"sources":[{"title":"TSMC CoWoS advanced packaging","url":"https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm"},{"title":"TSMC research: High Performance, High Density RDL","url":"https://research.tsmc.com/page/off-chip-interconnect/19.html"},{"title":"MIT: Communication System Design, interconnect and wire scaling","url":"https://ocw.mit.edu/courses/6-973-communication-system-design-spring-2006/44d1cff68d0f994cca25442de3e1ac78_lecture_5.pdf"}],"scale":"Millimeter-to-centimeter interposer with micrometer-scale routing","kind":"peelable-routing-layers","mechanism":["Fine-pitch terminals from logic and memory land on the dense interconnect platform.","Patterned routing layers carry many short lateral connections between neighboring dies and memory stacks.","Other routes transition toward the package substrate, which connects the integrated assembly to its wider system."],"misconception":"Not every interposer is one uniform silicon sheet. CoWoS variants can use silicon, redistribution layers, and local silicon interconnects in different constructions.","check":{"question":"What is the interposer’s central contribution to an AI accelerator?","options":["It executes the operating system.","It provides dense local routing between logic dies and memory.","It replaces all cooling equipment."],"answer":1,"explanation":"High-bandwidth memory needs a large number of nearby connections to the processor. Dense package routing makes those connections physically practical."},"branch":"Advanced packaging","subbranch":"Lateral routing","science":[{"title":"Long resistive routes can become disproportionately slow","equation":"tdelay ∝ R′ × C′ × ℓ²","explanation":"R′ and C′ are resistance and capacitance per unit length; ℓ is route length. In a distributed RC approximation, doubling a comparable unbuffered route can increase its delay by about four times. Dense package integration shortens routes between logic and memory and can reduce capacitance as well as physical distance, helping explain its performance and energy value.","assumptions":"RC-dominated, uniform unbuffered interconnect with fixed cross-section and loading convention. High-speed package channels can require transmission-line and full electromagnetic models; the proportionality is not a measured interposer delay specification."}],"history":[{"year":2012,"title":"TSMC CoWoS enters volume production","significance":"TSMC dates CoWoS volume production to 2012. The packaging platform evolved to integrate multiple logic dies and high-bandwidth memory through dense local interconnect, making the package an important part of system architecture.","source":{"title":"TSMC: CoWoS platform history and technology","url":"https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm"}}],"learningObjective":"Explain why longer package wiring has an RC cost.","engineeringExample":"If both distributed R′ and C′ stay constant, doubling the route length increases the simple delay proportional to length squared.","evidenceNotes":"The relation is a distributed-line intuition, not a package timing signoff.","visualFamily":"package-route","prerequisites":["interconnect","through-silicon-via"],"labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}