{"id":"interface-signal-eye","level":"infrastructure","name":"Signal integrity, timing and the eye diagram","shortName":"Signal integrity, timing and the eye diagram","role":"Tests whether a receiver can distinguish transmitted symbols under actual channel conditions.","description":"A digital link uses analog voltages or currents to encode symbols. Wires, connectors and package transitions attenuate and distort those signals; neighboring activity and supply noise add interference. A receiver needs enough voltage separation and timing margin to decide correctly. An eye diagram overlays many symbol intervals to reveal the available opening, while bit-error measurements test actual outcomes under stated conditions. Equalization can compensate for some channel loss but adds complexity and power. The IBM BoW interface study is a concrete example of signal and power analysis tied to a particular package implementation.","specs":[{"label":"Eye opening","value":"Voltage and time margin","context":"Volts and seconds at a stated measurement point."},{"label":"Error rate","value":"Errors / tested bits","context":"Test duration and statistical confidence matter, especially with no observed errors."}],"interfaces":[{"name":"Transmitter and channel","direction":"in","signal":"Symbols distorted by channel loss, reflections and crosstalk"},{"name":"Receiver decision","direction":"out","signal":"Recovered symbols and observed error events"}],"tradeoff":"Higher signaling rate or denser routing can raise bandwidth while reducing margin; equalization and extra spacing cost power or area.","whyAI":"Correct arithmetic is useless if package or network links corrupt data, retry excessively or fail under high simultaneous activity.","related":["interconnect","die-link-compatibility","power-integrity-budget"],"sources":[{"title":"Signal and Power Integrity Design and Analysis for BoW Interface for Chiplet Integration on Advanced Packaging","url":"https://research.ibm.com/publications/signal-and-power-integrity-design-and-analysis-for-bunch-of-wires-bow-interface-for-chiplet-integration-on-advanced-packaging"}],"scale":"Micrometers of package wiring to board-scale links; schematic","kind":"architecture","branch":"Chip-to-hall integration","subbranch":"Interface compatibility and electrical budgets","mechanism":["Define the channel, symbol rate, receiver requirements and environmental conditions.","Model or measure loss and reflections through each physical transition.","Include aggressor activity, timing jitter and supply noise in the margin analysis.","Inspect the received eye and measure errors with a documented test pattern and duration.","Adjust routing, termination or equalization and repeat integrated testing over operating corners."],"misconception":"An ideal square-wave drawing is not a measured signal; zero errors in a short test does not prove a zero error probability.","check":{"question":"Why can a link pass alone but fail beside busy neighbors?","options":["Bits change their mathematical definition","Channel behavior never depends on activity","Crosstalk or shared supply noise can reduce margin"],"answer":2,"explanation":"Neighboring transitions can disturb voltage or timing even though the intended logical data is unchanged."},"science":[{"title":"Unit interval","equation":"UI = 1 / Rsymbol","explanation":"Rsymbol is symbols/s and UI is seconds/symbol. Multi-level signaling may encode multiple bits per symbol.","assumptions":"Symbol rate and bit rate must not be conflated; coding and overhead affect payload rate."}],"prerequisites":["interconnect","clock"],"learningObjective":"Relate digital error behavior to analog channel and timing margins.","workstream":"W09","visualFamily":"signal-power","engineeringExample":"Synthetic 10 Gsymbol/s link has a 100 ps unit interval. A 20 ps total timing uncertainty consumes one fifth of that interval before considering the receiver’s own requirements.","evidenceNotes":"IBM’s numerical geometry results are not transferred to this example. Eye limits and test confidence must be specified for the actual interface.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}