{"id":"interconnect","level":"logic","name":"On-chip metal and via hierarchy","shortName":"Interconnect","role":"Connects cells through a multilayer electrical network.","description":"A chip's metal stack turns individual circuits into a system. Short local lines connect nearby devices, while higher-level wiring can span larger regions; vias join selected levels. The layout is a routed network with physical resistance, capacitance, congestion, and reliability limits. Consequently, a logically short connection is not automatically fast or inexpensive. The atlas pulls the wiring layers apart while keeping their vertical vias connected, revealing how many paths cross without electrical contact. Each wire must terminate at the correct node, and its surroundings affect its signal. This hierarchy is one reason adding more arithmetic units does not guarantee proportional application speed: the units must exchange operands and results.","specs":[{"label":"Connections","value":"Lines + vias","context":"Lateral routing and vertical level changes."},{"label":"Delay mechanism","value":"Resistance and capacitance","context":"Wire geometry and material influence both."},{"label":"Scaling issue","value":"Higher narrow-wire resistance","context":"Documented concern in advanced-node interconnect research."}],"interfaces":[{"name":"Cell outputs","direction":"in","signal":"Signal voltages and supply currents"},{"name":"Destination cells","direction":"out","signal":"Routed electrical connectivity"}],"tradeoff":"More routing capacity uses area and layers. Narrower wiring may worsen resistance and signal delay.","whyAI":"AI computation moves values between memory and arithmetic. Interconnect cost makes placement and data reuse essential.","related":["copper-conductor","dielectric","contact","standard-cell","sram","clock","on-chip-network"],"sources":[{"title":"IBM Research — Interconnect Performance and Scaling Strategy","url":"https://research.ibm.com/publications/interconnect-performance-and-scaling-strategy-at-the-5-nm-node"}],"scale":"Local nanometer features extending across millimeter-scale dies","kind":"interconnect","mechanism":["Route a cell’s output through a chosen conductive layer.","Use vias when a connection needs to move to another layer.","Deliver the signal to the correct destination while meeting resistance, capacitance, and routing constraints."],"misconception":"Crossing lines in different metal layers are not connected unless the design provides the appropriate vertical connection.","check":{"question":"Why can placing arithmetic near its operands help?","options":["It can reduce data-movement distance and interconnect cost","It removes every arithmetic operation","It makes memory contents independent of power"],"answer":0,"explanation":"Real wires have delay and energy costs. Data locality reduces some of the movement surrounding useful arithmetic."},"branch":"Materials and wiring","subbranch":"Routing hierarchy","science":[{"title":"Distributed wire-delay scaling","equation":"R = rL; C = cL; τ_wire ∝ rcL²","explanation":"For an unbuffered uniform wire, both resistance and capacitance grow with length, giving a quadratic length dependence in a simple RC model. This makes physical placement matter.","assumptions":"Distributed RC approximation with per-length r and c; driver resistance, repeaters, coupling, and inductance can change the actual delay law."}],"history":[],"prerequisites":["copper-conductor","dielectric"],"learningObjective":"Use a distributed RC approximation to explain why a longer unbuffered wire can have more than a proportional delay cost.","engineeringExample":"Synthetic wire: r = 0.1 Ω/μm and c = 0.2 fF/μm over 100 μm give R = 10 Ω, C = 20 fF and RC = 200 fs. At 200 μm, R = 20 Ω and C = 40 fF, so RC = 800 fs. The product quadruples; the actual delay includes the model-dependent coefficient and driver.","evidenceNotes":"The linked interconnect work motivates resistance/capacitance scaling. Synthetic values illustrate an unbuffered uniform RC line, not a node-specific delay prediction; repeaters, coupling and inductance can change the result.","labId":"library","scope":"Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.","investigationId":"switching","labScope":"Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism."}