{"id":"hbm-stack-thermal-yield","level":"package","name":"HBM heat, assembly yield and test access","shortName":"HBM heat, assembly yield and test access","role":"Explain how added layers affect the heat path, screening strategy and delivered good stacks.","description":"Every added die introduces heat sources, interfaces and opportunities for assembly damage. Heat follows several parallel paths through silicon, metal, polymer and the surrounding package; the hottest location is not necessarily the tallest die. Test coverage changes with access: a wafer test can inspect some die functions before stacking, while TSV chains, cross-die connections and the complete high-speed interface require later checks. A known-good input is a unit that passed a defined screen, not a physically perfect die. Assembly yield therefore starts from screened inputs and counts newly introduced failures, avoiding a second charge for the same wafer loss.","mechanism":["Define incoming wafer/die test coverage and preserve identity through thinning, singulation and stacking.","Measure continuity and functional behavior at the stages where test access exists; map errors to the same stack genealogy.","Estimate heat from each active layer using a stated power distribution and boundary temperature.","Inspect assembly defects with electrical tests plus suitable imaging; a hot spot or open circuit alone does not identify its cause.","Separate per-unit screening, product reliability qualification and observed in-service failure rates."],"science":[{"title":"Multiple heat sources","equation":"Ti − Tcoolant = Σj Rij Pj","explanation":"A thermal-resistance matrix represents how each heat source j contributes to temperature at location i, including cross-heating.","assumptions":"Linear steady-state approximation at specified boundaries. Transients and temperature-dependent properties require a richer model."},{"title":"Conditional assembly yield","equation":"Yassembly ≈ yjoint^J","explanation":"J is the number of independently modeled assembly interfaces, each with aggregate conditional pass probability yjoint.","assumptions":"Screened inputs; excludes residual input escapes, correlated defects, repair and common tooling failures. An interface probability is not a per-bump probability."}],"specs":[{"label":"Yield denominator","value":"Screened input sets","context":"Do not multiply their original wafer yield a second time."},{"label":"Thermal boundary","value":"Location, power map and coolant","context":"Stack-average temperature can hide local limits."}],"interfaces":[{"name":"Die screening","direction":"in","signal":"Coverage, bin and residual escape risk"},{"name":"Stack test","direction":"out","signal":"Functional, interconnect and thermal evidence"}],"tradeoff":"Earlier screening avoids wasting downstream components, but adds handling, test time and cost; some failures are only observable after assembly.","whyAI":"Effective stack supply and sustainable frequency depend on both manufacturability and thermal operation.","prerequisites":["hbm-stack-height-budget","known-good-die-test"],"related":["package-thermomechanical-reliability","memory-system-qualification","hbm-stack-assembly-test"],"misconception":"Track the denominator at each stage; conditional assembly loss acts on the units that actually enter assembly.","check":{"question":"Why not multiply wafer yield into every already screened die again?","options":["It double-counts losses already excluded from the incoming population","Screening guarantees zero future failures","HBM assembly cannot introduce faults"],"answer":0,"explanation":"Track the denominator at each stage; conditional assembly loss acts on the units that actually enter assembly."},"engineeringExample":"Synthetic independent-interface model: 12 interfaces at 99.5% conditional pass probability yield about 94.2%; at 99.9%, about 98.8%. A shared contamination event violates independence. These values do not estimate any supplier’s yield.","evidenceNotes":"imec’s 2025 thermal study concerns a specified research HBM-on-GPU arrangement. It motivates spatial heat analysis; its simulated temperatures are not general product limits.","sources":[{"title":"imec — thermal STCO study of 3D HBM-on-GPU","url":"https://www.imec-int.com/en/press/imec-mitigates-thermal-bottleneck-3d-hbm-gpu-architectures-using-system-technology-co"},{"title":"MIT OpenCourseWare — Introduction to Heat Transfer","url":"https://ocw.mit.edu/courses/2-051-introduction-to-heat-transfer-fall-2015/"},{"title":"SK hynix — the team behind 12-layer HBM3","url":"https://news.skhynix.com/en/meet-the-sk-hynix-team-behind-the-worlds-first-12-layer-hbm3/"}],"learningObjective":"Explain how added layers affect the heat path, screening strategy and delivered good stacks.","workstream":"W06","visualFamily":"hbm-detail","scale":"Thermal path and test population across a memory stack; schematic","kind":"process","labId":"hbm-stack-build","branch":"Memory","subbranch":"HBM height, heat and test closure","scope":"Adjust stack layers, thickness, joint route, interface bandwidth and conditional yield; presets are synthetic, not supplier process windows.","investigationId":"manufacturing","labScope":"Adjust stack layers, thickness, joint route, interface bandwidth and conditional yield; presets are synthetic, not supplier process windows."}