{"id":"hbm-silicon-intensity","level":"package","name":"HBM silicon intensity and allocation","shortName":"HBM silicon intensity and allocation","role":"Estimates wafer demand per delivered bit without double-counting embedded yield losses.","description":"HBM requires silicon for memory arrays, peripheral circuits, vertical connections and base-die functions, followed by thinning, stacking and test. A stack’s footprint hides the area of its multiple dies. Silicon intensity can mean geometric area per bit or empirical wafer supply per delivered bit: different accounting methods. The geometric route explicitly applies relevant yields. An empirical ratio may already include those losses and must not receive them again. This lesson converts memory requirements into a consistent supply boundary with a dated supplier comparison whose denominator is kept explicit.","specs":[{"label":"Geometric method","value":"Area per gross bit plus explicit yields","context":"Separate memory and logic-process base-die wafer requirements."},{"label":"Empirical method","value":"Wafer supply per delivered bit","context":"State generation, node, output boundary and included losses."},{"label":"Different quantities","value":"Footprint, summed silicon area and delivered capacity","context":"Stack height and package area alone cannot measure wafer demand."}],"interfaces":[{"name":"Memory requirement and scoped model","direction":"in","signal":"Target bits, product configuration and nonoverlapping yield/intensity assumptions"},{"name":"Normalized manufacturing demand","direction":"out","signal":"Wafer-equivalent or good-stack requirements over a stated period"}],"tradeoff":"More capacity or bandwidth can consume additional wafer and assembly resources; architecture and memory-traffic improvements can reduce demand.","whyAI":"HBM can limit deployable accelerators even when logic wafers are available, connecting model memory requirements to manufacturing allocation.","related":["yield-wafer-defect-model","hbm-stack-assembly-test","hbm-channel-generation-ras","fab-ramp-cycle-time"],"sources":[{"title":"Micron — FY Q2 2024 prepared remarks, page 6","url":"https://micron.gcs-web.com/static-files/1a8d6c22-3b89-4806-930c-d30cbcd270d5"},{"title":"SK hynix — TSMC collaboration on HBM","url":"https://news.skhynix.com/en/sk-hynix-partners-with-tsmc-to-strengthen-hbm-technological-leadership/"},{"title":"DISCO — Tech Briefing 2023","url":"https://disco.co.jp/jp/ir/movie/doc/E_Tech_Briefing_2023.pdf"},{"title":"Micron — HBM3E","url":"https://www.micron.com/products/memory/hbm/hbm3e"}],"scale":"Memory channels, package links and wafer-supply accounting","kind":"integration","branch":"Memory / HBM system constraints","subbranch":"HBM interfaces, generations and silicon intensity","mechanism":["Specify gross, good-die, tested-stack or package-delivered bits as the output boundary.","For geometry, sum die area and apply explicitly defined, nonoverlapping yield losses.","For empirical intensity, determine which wafer-to-output losses the reported ratio already includes.","Calculate separate memory and base-die process demands without applying any loss twice.","Compare stack demand with logic, substrate and assembly constraints before predicting delivered accelerators."],"misconception":"Wafer-supply intensity is neither package footprint nor a universal multiplier across HBM generations.","check":{"question":"When is applying an extra stack-yield penalty to an empirical wafer/output-bit ratio justified?","options":["Never for any geometric model either","Only when that ratio demonstrably excludes the stack loss","Always, because more factors improve accuracy"],"answer":1,"explanation":"The starting metric’s denominator and included losses determine which additional factors are legitimate."},"science":[{"title":"Two alternative demand models","equation":"Geometric: W ≈ B_target a_bit/(A_usable Y); empirical: W = B_target I_emp","explanation":"B_target is target output bits, a_bit gross silicon area/bit, A_usable effective wafer area, Y the explicitly modeled nonoverlapping survival, and I_emp wafers/output bit.","assumptions":"Account separately for packing, redundancy and logic-process base dies; do not combine these alternative formulas blindly."}],"prerequisites":["yield-wafer-defect-model","hbm-stack-assembly-test"],"learningObjective":"Choose a consistent HBM silicon-intensity method and avoid duplicated yield penalties.","workstream":"W06","visualFamily":"capacity-flow","engineeringExample":"Synthetic empirical case: two wafer-equivalents per unit of tested-stack bits and ten units of demand require twenty wafer-equivalents. Applying a stack yield already embedded in that intensity would overstate demand.","evidenceNotes":"Micron’s March 20, 2024 prepared remarks, page 6, report approximately 3× wafer supply for HBM3E versus DDR5 at equal bits and the same technology node. This historical supplier statement does not establish a universal generation-independent factor, package footprint or current customer allocation. The lab keeps synthetic inputs and does not add losses already embedded in an empirical ratio.","labId":"engineering","scope":"Compare a synthetic geometric area ratio with an output-normalized supply ratio without applying the same yield loss twice.","deepLabId":"hbm","investigationId":"manufacturing","labScope":"Compare a synthetic geometric area ratio with an output-normalized supply ratio without applying the same yield loss twice."}