{"id":"hbm-hybrid-bond-route","level":"package","name":"Hybrid bonding: surface-to-interface closure","shortName":"Hybrid bonding: surface-to-interface closure","role":"Follow CMP, cleaning, alignment, contact and anneal as one surface-controlled integration problem.","description":"Hybrid bonding joins a dielectric interface together with matching conductive pads. The goal is a dense direct connection without a solder-bump gap at that interface. Surface flatness alone is insufficient: local copper topography, surface chemistry, particles, placement error and the thermal cycle determine whether the two material systems can join as intended. A wafer-to-wafer process and a die-to-wafer process have different handling, selection and throughput constraints. A successful research pitch demonstration establishes a result on its specified test structure; it does not establish that a complete HBM product is shipping with that process.","mechanism":["Form patterned bonding metal and dielectric, then planarize to a controlled local topography.","Measure copper recess, surface roughness and within-wafer variation; clean and prepare the bonding surfaces.","For a die route, preserve the prepared surface through singulation and handling; retain the known-good input map.","Align and contact according to the chosen route, then complete the required anneal for the bonded interface.","Assess electrical chains, voids, alignment and mechanical integrity, and qualify the full product separately."],"science":[{"title":"Geometric pad-overlap example","equation":"Aoverlap = max(0,w−|dx|) max(0,w−|dy|)","explanation":"For equal square pads, misalignment reduces geometrical overlap in both axes. Electrical yield also depends on surface and material behavior.","assumptions":"Rigid planar equal squares; no rotation, deformation or local overlay field. This is not a qualified bond tolerance."}],"specs":[{"label":"Surface condition","value":"Local topography and chemistry","context":"A mean wafer flatness value cannot certify every bond interface."},{"label":"Route distinction","value":"Wafer-to-wafer versus die-to-wafer","context":"Do not transfer one route’s pitch/throughput claim to the other."}],"interfaces":[{"name":"Prepared metal/dielectric surface","direction":"in","signal":"Measured topography, cleanliness and pad position"},{"name":"Bonded interface","direction":"out","signal":"Electrical, dielectric and mechanical continuity"}],"tradeoff":"Finer direct interconnects can reduce spacing, but surface preparation, handling and overlay increase integration demands; solder self-alignment cannot be assumed.","whyAI":"The available interface pitch and thermal/mechanical envelope constrain future memory-on-logic arrangements.","prerequisites":["hybrid-bond-surface-alignment","hbm-stack-height-budget"],"related":["hbm-tc-ncf-route","hbm-mr-muf-route","hbm-bonding-process-selection","clean-planarize-surface"],"misconception":"Bond success depends on local conditions and the integrated route; one average cannot settle all failure mechanisms.","check":{"question":"A clean-looking surface has acceptable mean flatness. Is that sufficient evidence of good hybrid bonds?","options":["No: local topography, chemistry, alignment and bonded-interface tests remain necessary","Yes: average flatness certifies all electrical connections","Yes: annealing removes every particle"],"answer":0,"explanation":"Bond success depends on local conditions and the integrated route; one average cannot settle all failure mechanisms."},"engineeringExample":"Synthetic equal square pads of width 2 µm offset 0.2 µm in x and y retain 3.24 µm² overlap, 81% of the nominal area. This geometric result is neither an 81% bond yield nor a recommended pad design.","evidenceNotes":"imec sources establish wafer-to-wafer and die-to-wafer research mechanisms. Product-specific HBM hybrid-bond qualification, throughput and cost are not inferred.","sources":[{"title":"imec — wafer-to-wafer hybrid bonding at 400 nm pitch","url":"https://www.imec-int.com/en/articles/wafer-wafer-hybrid-bonding-pushing-boundaries-400nm-interconnect-pitch"},{"title":"imec — die-to-wafer hybrid bonding demonstration","url":"https://www.imec-int.com/en/press/imec-demonstrates-die-wafer-hybrid-bonding-cu-interconnect-pad-pitch-2mm"}],"learningObjective":"Follow CMP, cleaning, alignment, contact and anneal as one surface-controlled integration problem.","workstream":"W05","visualFamily":"hbm-detail","scale":"Bond surface nanometers to die placement micrometers; dimensions exaggerated","kind":"process","labId":"hbm-stack-build","branch":"Packaging","subbranch":"HBM bonding routes and process closure","scope":"Adjust stack layers, thickness, joint route, interface bandwidth and conditional yield; presets are synthetic, not supplier process windows.","investigationId":"manufacturing","labScope":"Adjust stack layers, thickness, joint route, interface bandwidth and conditional yield; presets are synthetic, not supplier process windows."}