{"id":"hbm-bonding-process-selection","level":"package","name":"Selecting a bonding route under constraints","shortName":"Selecting a bonding route under constraints","role":"Compare qualified output, height, thermal behavior, inspection and cost on the same product boundary.","description":"A useful process comparison starts from one required product: die count, footprint, electrical interfaces, operating conditions and test coverage. TC-NCF, MR-MUF and hybrid bonding organize joint formation and support differently. Each route moves effort among surface preparation, die placement, joint formation, encapsulation, annealing and inspection. “Finer pitch” and “faster bond tool” are individual attributes, not complete cost or delivery answers. Keep development readiness and demonstrated results beside each route, and leave supplier yield, process time or commercial price unknown when undisclosed.","mechanism":["Fix the same functional memory requirement and package-height boundary before comparing alternatives.","Map the chosen route’s preparation, handling, bonding/fill, thermal and test steps without replacing them with one generic bond operation.","Define compatible station capacity and conditional yield for the same input population.","Include consumables, equipment occupancy, inspection and losses in a cost per accepted stack model.","Reject or revise routes that miss electrical, thermal, mechanical or qualification requirements even if nominal throughput is high."],"science":[{"title":"Cost per accepted stack","equation":"cgood = (cinput + cprocess + ctest) / Y","explanation":"Costs are normalized to one assembled input set and divided by final pass fraction.","assumptions":"Simple no-rework average with all modeled costs incurred per input set; stage-dependent scrap/rework requires a yield waterfall."}],"specs":[{"label":"Comparison basis","value":"Same product and test coverage","context":"Different layer counts or qualification stages are not an equal comparison."},{"label":"Readiness","value":"Research, sample, qualified, production","context":"Keep date and measured scope visible."}],"interfaces":[{"name":"Process candidate","direction":"in","signal":"Flow, equipment and material requirements"},{"name":"Integration decision","direction":"out","signal":"Feasible route plus remaining evidence needs"}],"tradeoff":"Reducing joint thickness can consume more surface-control effort; reducing bond time may expose inspection or supply as the next bottleneck.","whyAI":"Memory economics and supply depend on accepted output from the complete route, affecting how many accelerators can be deployed.","prerequisites":["hbm-tc-ncf-route","hbm-mr-muf-route","hbm-hybrid-bond-route"],"related":["hbm-silicon-intensity","compatible-supply-capacity","crg-package-system-closure"],"misconception":"A process must close the full product and production requirements; one favorable parameter does not establish a usable stack.","check":{"question":"Which comparison supports an engineering choice?","options":["Same product boundary, yield denominator and qualification requirements","Only minimum reported pitch","Only the fastest advertised bonding operation"],"answer":0,"explanation":"A process must close the full product and production requirements; one favorable parameter does not establish a usable stack."},"engineeringExample":"Synthetic routes: 100 currency units per input set at 90% final yield cost 111.1 per accepted stack. A 105-unit route at 97% costs 108.2. The example illustrates sensitivity; it ranks no commercial process.","evidenceNotes":"Route mechanisms are grounded in their named sources. Cost, cycle time and yield values in the workbench are transparent teaching scenarios, not supplier disclosures.","sources":[{"title":"Samsung — 36 GB HBM3E 12H development","url":"https://news.samsung.com/global/samsung-develops-industry-first-36gb-hbm3e-12h-dram"},{"title":"SK hynix — Small Size, Big Impact","url":"https://news.skhynix.com/en/small-size-big-impact/"},{"title":"imec — wafer-to-wafer hybrid bonding at 400 nm pitch","url":"https://www.imec-int.com/en/articles/wafer-wafer-hybrid-bonding-pushing-boundaries-400nm-interconnect-pitch"}],"learningObjective":"Compare qualified output, height, thermal behavior, inspection and cost on the same product boundary.","workstream":"W05","visualFamily":"package-route","scale":"Process-flow alternatives on a fixed stack/package boundary; schematic","kind":"process","labId":"hbm-stack-build","branch":"Packaging","subbranch":"HBM bonding routes and process closure","scope":"Adjust stack layers, thickness, joint route, interface bandwidth and conditional yield; presets are synthetic, not supplier process windows.","investigationId":"manufacturing","labScope":"Adjust stack layers, thickness, joint route, interface bandwidth and conditional yield; presets are synthetic, not supplier process windows."}