{"id":"graph-tensor-ir","level":"software","name":"Model graph and tensor intermediate representation","shortName":"Model graph and tensor intermediate representation","role":"Preserves operation semantics before committing to a device instruction schedule.","description":"A framework expresses a model as tensor operations and control flow. A compiler front end captures an appropriate portion of that program into an intermediate representation, recording shapes, element types and dependencies. StableHLO is one public operation specification used between frameworks and compilers; it describes what operations mean, not which physical unit must execute them. A matrix multiplication followed by bias and activation may begin as several graph nodes. These can later be transformed or fused if their semantics allow it. Dynamic shapes and data-dependent control can require specialization, runtime decisions or boundaries between compiled regions.\n\nA graph representation can carry shapes and operator semantics while leaving memory placement and execution schedules unresolved. When this graph is lowered, each representation needs a checkable relation to the same intended output. Equal array dimensions do not establish equal axis meaning. Explicit input/output examples and value ownership let a reader determine what was preserved instead of treating a compiler stage as a decorative box.","specs":[{"label":"Tensor type","value":"Shape plus element representation","context":"Logical shape does not fix physical strides or memory location."},{"label":"Graph edge","value":"Value dependency","context":"A software graph is not a wiring diagram of a processor."}],"interfaces":[{"name":"Framework program","direction":"in","signal":"Tensor operators, parameters and control dependencies"},{"name":"Compiler IR","direction":"out","signal":"Typed operations with explicit dataflow and shape constraints"}],"tradeoff":"More shape specialization enables optimization but creates additional compiled variants and potential compilation delay when new shapes appear.","whyAI":"The graph connects model intent to executable work; unsupported operations and graph breaks can move data or execution back to the host.","related":["compiler","compiler-layout-lowering","embedding","coding-agent-patch-evidence"],"sources":[{"title":"StableHLO specification","url":"https://openxla.org/stablehlo/spec"}],"scale":"Software abstraction layers mapped to physical memory and compute","kind":"workload","branch":"Model–machine co-design","subbranch":"Graph to executable operation","mechanism":["Identify the model region captured for compilation and the inputs whose shapes or values remain dynamic.","Represent operators with defined semantics, including broadcasting, reductions and numerical element types.","Record producer-to-consumer dependencies so transformations preserve the required result.","Apply legal simplifications such as eliminating unused results or combining constant expressions.","Pass a typed graph to device-aware lowering while retaining enough provenance to relate optimized operations back to the model.","The graph declares which axes are contracted, broadcast or retained before any physical buffer is chosen.","A lowered implementation is compared against an independent reference on a stated arithmetic domain and input set."],"misconception":"One framework operation does not necessarily become one kernel, one instruction or one dedicated hardware block.","check":{"question":"What does a tensor type of shape 4×8 establish by itself?","options":["The logical element dimensions","The exact GPU addresses and strides","The number of physical tensor cores used"],"answer":0,"explanation":"The shape describes logical indexing; memory layout and hardware mapping are later choices or separately specified properties."},"science":[{"title":"Logical tensor size","equation":"Mlogical = s × Πi di","explanation":"di counts elements along dimension i and s is bytes per stored element; Mlogical is bytes.","assumptions":"Dense unpadded representation; metadata, alignment, sparse encoding and replication can change allocated size."}],"prerequisites":["compiler","kernel"],"learningObjective":"Distinguish graph semantics, tensor types and physical execution mapping.","workstream":"W11","visualFamily":"software-flow","engineeringExample":"Synthetic graph: Y = maximum(XW + b, 0) contains a dot, broadcasted bias add and activation. With X of shape 4×8 and two-byte elements, X has 64 logical bytes before padding or replication.\n\nFor X=[[1,2]] and W=[[3],[4]], XW is [[11]]. Adding bias −12 and applying ReLU gives [[0]]. Applying ReLU before adding the bias instead gives [[−1]], so moving operations because their intermediate shapes match changes the function. A legal fusion can eliminate materialized intermediates only while preserving the specified order and result.","evidenceNotes":"StableHLO is a named reference path. Other stacks have different capture rules and IRs; portability of meaning does not imply identical performance or binary compatibility.\n\nThe arithmetic is an authored exact example. It does not claim that a real compiler performs this invalid transformation or that a new compiler implementation has been executed.","checks":[{"question":"Can operations be reordered merely because their intermediate shapes match?","options":["Yes, shape equality proves semantic equality","No, the function and dependencies must be preserved","Yes, if all operators use the same dtype"],"answer":1,"explanation":"The bias/ReLU example has the same shapes but a different output after reordering."}],"labId":"library","scope":"Use the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.","investigationId":"execution","labScope":"Use the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism."}