{"id":"fin-formation-integration","level":"transistor","name":"How a FinFET fin is formed and integrated","shortName":"How a FinFET fin is formed and integrated","role":"Turns a three-dimensional silicon ridge into a controlled transistor channel.","description":"A FinFET obtains stronger gate control by placing the gate around multiple sides of a narrow silicon fin. The device geometry must be manufactured before it can provide that advantage. Patterning defines the fin location; etching establishes height and sidewalls; isolation fill and recess expose the intended channel portion. Gate and source/drain modules then complete a transistor around the preserved fin. Width, height, roughness and stress all matter, and their influence differs from simply drawing a narrower planar channel. The lesson follows one fin through the sequence so that isolated process steps remain connected to the final electrical path.","specs":[{"label":"Channel geometry","value":"Fin height, width and exposed sidewalls","context":"Dimensions refer to named material boundaries after defined steps."},{"label":"Width control","value":"Integer fin count in many designs","context":"Effective drive width and physical layout width are different quantities."}],"interfaces":[{"name":"Patterned active region","direction":"in","signal":"Fin position and surrounding isolation plan"},{"name":"Fin channel","direction":"out","signal":"Three-dimensional semiconductor body ready for gate integration"}],"tradeoff":"Taller or narrower fins can improve density or electrostatics while increasing etch, variability and mechanical integration demands.","whyAI":"FinFET manufacturing enabled dense high-performance logic used across processors and accelerators; process variation changes usable frequency and leakage bins.","related":["finfet","wells-isolation-integration","source-drain-contact-integration"],"sources":[{"title":"Applied Materials — New Ways to Shrink","url":"https://ir.appliedmaterials.com/static-files/f2fbf48d-a761-4c4f-ab4c-73f312ab1ebc"},{"title":"MIT 6.152J — Micro/Nano Processing Technology lecture notes","url":"https://ocw.mit.edu/courses/6-152j-micro-nano-processing-technology-fall-2005/pages/lecture-notes/"},{"title":"Intel — Reinvents Transistors Using New 3-D Structure","url":"https://www.intc.com/news-events/press-releases/detail/655/intel-reinvents-transistors-using-new-3-d-structure"}],"scale":"Nanometer device cross-sections; reference flow with alternatives","kind":"process","branch":"Fabrication / FEOL and MOL","subbranch":"Integrating the transistor","mechanism":["Pattern the fin arrangement using the chosen lithography and pattern-transfer route.","Etch the semiconductor to establish fin height and sidewall profile.","Fill surrounding isolation and recess it to expose the desired channel surfaces.","Form the gate module around the accessible fin surfaces and integrate spacers and source/drain regions.","Measure fin geometry and completed-device behavior to connect structural variation with electrical results."],"misconception":"A process node name does not specify the fin width, and fin width alone does not determine transistor drive.","check":{"question":"Why does fin-height variation matter even if the top-view linewidth is correct?","options":["It changes the gate-controlled channel perimeter and integration geometry","Only top-view dimensions affect a FinFET","It changes silicon into copper"],"answer":0,"explanation":"Current can flow along multiple gated surfaces, so a two-dimensional top view is incomplete."},"science":[{"title":"Geometric effective-width estimate","equation":"W_eff ≈ N_f(2H_f + W_f)","explanation":"Fin count N_f is dimensionless; exposed fin height H_f and top width W_f use length units.","assumptions":"A tri-gate geometric approximation. Different surface mobilities, corner effects and electrostatics prevent exact current prediction from perimeter alone."}],"prerequisites":["finfet","plasma-wet-etch-transfer"],"learningObjective":"Connect fin formation and isolation recess to a FinFET’s controlled surfaces.","workstream":"W03","visualFamily":"device-crosssection","engineeringExample":"Synthetic geometry: two fins with H_f = 30 nm and W_f = 8 nm give a perimeter estimate of 136 nm. This is effective gated width, not the cell footprint or a measured current.","evidenceNotes":"Sequence is representative. Fin counts, dimensions and material recipes are illustrative, with no claim about a particular production node.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}