{"id":"fab-ramp-cycle-time","level":"die","name":"Cycle time, ramp and effective capacity","shortName":"Cycle time, ramp and effective capacity","role":"Connects tool throughput, queues, qualification and yield learning over time.","description":"A factory’s output changes during ramp. Equipment is installed and qualified, process capability stabilizes, staffing and maintenance practices mature, and product yield evolves. Nameplate tool throughput describes only part of that path. Re-entrant processing and shared bottlenecks create waiting time between operations, while engineering holds and qualification gates can stop release. Wafer starts, work in process and good dies shipped are therefore different time-series quantities. The lesson follows a batch through a simple factory and asks which constraint determines completed output today, then separates announced future capacity from operating and product-qualified capacity.","specs":[{"label":"Flow metrics","value":"Starts, WIP, throughput and cycle time","context":"Use a common material boundary and calendar interval."},{"label":"Capacity state","value":"Installed → qualified → producing → released","context":"Each transition requires evidence; dates can differ."}],"interfaces":[{"name":"Qualified routes and resources","direction":"in","signal":"Tools, utilities, materials, labor and release criteria"},{"name":"Released output","direction":"out","signal":"Good units available after their actual process and test history"}],"tradeoff":"Running near full utilization can build queues and increase cycle time; spare capacity can absorb variation but costs money.","whyAI":"The synchronization of good logic dies, HBM, substrates and package capacity determines when accelerator demand can become delivered hardware.","related":["manufacturing-execution-dispatch","cleanroom-subfab-utilities","yield-wafer-defect-model","hbm-silicon-intensity"],"sources":[{"title":"TSMC — Intelligent Packaging Fab","url":"https://www.tsmc.com/english/dedicatedFoundry/services/apm_intelligent_packaging_fab"},{"title":"Edwards — Semiconductor vacuum and abatement","url":"https://www.edwardsvacuum.com/en-us/semiconductor"},{"title":"Advantest — Semiconductor test glossary","url":"https://www.advantest.com/en/investors/ir-library/glossary/"}],"scale":"Feature measurements, wafer maps and time-dependent production","kind":"process","branch":"Fabrication / Control, test and ramp","subbranch":"From processed wafers to released output","mechanism":["Separate installed equipment from capacity qualified for the intended product route.","Convert repeated tool visits and shared product demand to a consistent load basis.","Track work-in-process, queues, holds and departures over time.","Combine throughput with measured release yield using nonoverlapping denominators.","Update the binding constraint as tools, yields or downstream assembly readiness change."],"misconception":"A capacity announcement or a tool’s rated wafers/hour is not equivalent to good dies shipped per month.","check":{"question":"What happens if wafer starts rise while the final qualified bottleneck throughput stays fixed?","options":["WIP and cycle time can rise without more completed output","Good output must rise in exact proportion","Every wafer instantly becomes a package"],"answer":0,"explanation":"Additional incoming work accumulates unless another route or genuine bottleneck-capacity change handles it."},"science":[{"title":"Little’s law","equation":"WIP = throughput × cycle time","explanation":"WIP counts a consistent unit, throughput uses units/day and cycle time days, averaged over the same stable system.","assumptions":"Long-run stable flow with consistent boundaries. During ramp or a growing backlog, transient accounting is needed instead of naïve steady-state inference."}],"prerequisites":["manufacturing-execution-dispatch","yield-wafer-defect-model"],"learningObjective":"Interpret time-dependent manufacturing capacity without confusing starts and released output.","workstream":"W04","visualFamily":"fab-operations","engineeringExample":"Synthetic stable line: 500 wafers of WIP and 10 wafers/day throughput imply 50 days average cycle time. The equation does not prove a newly ramping line is already stable.","evidenceNotes":"Factory rates, costs, queues and ramp schedules are illustrative. Public capability pages do not provide a measured customer-level queue.","labId":"library","scope":"No current calculator directly models this lesson’s main mechanism. Use the library for related bounds while retaining their stated omissions.","investigationId":"manufacturing","labScope":"No current calculator directly models this lesson’s main mechanism. Use the library for related bounds while retaining their stated omissions."}