{"id":"fab-metrology-process-window","level":"die","name":"Metrology, inspection and process windows","shortName":"Metrology, inspection and process windows","role":"Measures geometry and defects at the stage where a manufacturing decision can still be made.","description":"Inspection asks where suspected defects are; metrology measures quantities such as thickness, critical dimension, overlay or shape. Both depend on sampling and a measurement system with finite uncertainty. A process window is the region of conditions that meets several requirements together, potentially including transferred geometry and electrical behavior. It is not defined by one attractive wafer image or one average value. Wafer, field, pattern and tool variation can overlap. This lesson aligns measurements to their process stages and populations, then chooses a follow-up capable of distinguishing competing explanations before changing a production process.","specs":[{"label":"Pattern metrics","value":"CD, overlay, roughness and defectivity","context":"Different variables; retain units, stage and population."},{"label":"Uncertainty","value":"Repeatability, bias and sampling","context":"A displayed number is not automatically the true feature value."}],"interfaces":[{"name":"Wafer and equipment history","direction":"in","signal":"Material state, sites, recipe and tool context"},{"name":"Control evidence","direction":"out","signal":"Measurements, defects and uncertainty for a release decision"}],"tradeoff":"More sensitive or denser measurement can reveal failures sooner but consumes time and may not sample every product-relevant feature.","whyAI":"Process control protects the large accumulated value of complex logic and memory flows and enables a stable yield ramp.","related":["resist-track-development","plasma-wet-etch-transfer","yield-wafer-defect-model"],"sources":[{"title":"KLA — Chip Manufacturing 101","url":"https://www.kla.com/wp-content/uploads/ChipManufacturing101.pdf"},{"title":"KLA — Practical Applications of Measurement System Analysis","url":"https://www.kla.com/documents/5.3_Practical_Applications_of_MSA_Sutherland_KLA.pdf"}],"scale":"Feature measurements, wafer maps and time-dependent production","kind":"process","branch":"Fabrication / Control, test and ramp","subbranch":"From processed wafers to released output","mechanism":["Define each response at an explicit process state and physical feature.","Check calibration, repeatability and sampling before interpreting a shift as a process change.","Retain spatial and tool/lot structure rather than collapsing immediately to an average.","Evaluate the intersection of requirements across tested conditions.","Choose a discriminating follow-up and verify the downstream result before asserting a causal fix."],"misconception":"A tight distribution from a biased measurement system can still miss the actual product target.","check":{"question":"Which comparison best tests whether an apparent tool shift is a metrology artifact?","options":["Matched samples measured with a controlled repeatability/reference study","Different products measured at unrelated stages","A single wafer image with no calibration"],"answer":0,"explanation":"A matched study can separate measurement variation from changes in the material population."},"science":[{"title":"Observed variance model","equation":"σ_obs² = σ_process² + σ_measurement²","explanation":"Variances use squared units of the response, such as nm².","assumptions":"Independent additive random-error approximation. Systematic bias and correlated errors are not removed by subtracting variances."}],"prerequisites":["lithography","cmp"],"learningObjective":"Interpret stage-specific process windows while accounting for measurement uncertainty.","workstream":"W04","visualFamily":"fab-operations","engineeringExample":"Synthetic measurement: 3 nm observed standard deviation and 2 nm independent metrology deviation imply √(9−4) ≈ 2.24 nm process deviation under the model. The calculation does not estimate an unknown measurement bias.","evidenceNotes":"Sampling rates and acceptance windows are product-specific. Simulated maps illustrate patterns and do not diagnose a real fab excursion.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}