{"id":"emib-local-bridge","level":"package","name":"EMIB and localized die-to-die bridges","shortName":"EMIB and localized die-to-die bridges","role":"Places fine-routing silicon near adjacent die edges inside a substrate.","description":"Intel’s EMIB uses embedded bridges to connect neighboring dies through a substrate-based assembly. Fine routing is concentrated at the relevant die-to-die boundaries instead of requiring one full-area silicon interposer. This changes where alignment, substrate construction and joint formation must succeed. A bridge is not an active processor merely because it is made of silicon. Public EMIB-T descriptions add through-silicon connections and power-delivery capabilities, so that variant must be labeled explicitly rather than silently drawn as original EMIB. Comparing bridge and interposer routes requires equivalent endpoints, power and test requirements, not a claim that eliminating one structure eliminates all package yield loss.","specs":[{"label":"Baseline EMIB","value":"Localized embedded routing bridge","context":"A package interconnect structure near adjacent dies."},{"label":"EMIB-T distinction","value":"TSV-enabled extension in Intel’s disclosure","context":"Roadmap and offering status require a dated configuration."}],"interfaces":[{"name":"Dies and bridge-bearing substrate","direction":"in","signal":"Compatible edge interfaces and qualified substrate structures"},{"name":"Connected multi-die package","direction":"out","signal":"Short local die-to-die paths plus substrate power/I/O routing"}],"tradeoff":"Localized routing can avoid a full-area interposer but shifts demands to bridge embedding, substrate accuracy and die placement.","whyAI":"Bridge routes can connect compute chiplets and memory in large packages while preserving a different manufacturing dependency structure.","related":["cowos-r-l-routing","flip-chip-abf-substrate","bump-thermocompression-assembly"],"sources":[{"title":"Intel Foundry — Accelerating HPC and AI","url":"https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf"}],"scale":"Multi-die package to selected joint; not dimensionally identical alternatives","kind":"integration","branch":"Packaging / Interposers, bridges and stacking","subbranch":"Alternative integration routes","mechanism":["Identify adjacent dies and the edge interfaces that require dense interconnection.","Fabricate and embed the corresponding bridge structures into the compatible substrate route.","Align each die to both its local bridge interface and other substrate connections.","Complete joints and package structures, then verify electrical continuity and stress behavior.","Label EMIB-T-specific TSV/power features separately when comparing that disclosed variant."],"misconception":"Eliminating a full silicon interposer does not eliminate substrate, bridge-placement or final assembly losses.","check":{"question":"Which information is needed before claiming an EMIB-specific capacity bottleneck?","options":["Any company-wide wafer capex number","A picture showing several bridges","Direct evidence scoped to that route and time period"],"answer":2,"explanation":"Route architecture does not provide a measured manufacturing queue or allocation."},"science":[{"title":"Connection-yield sensitivity","equation":"Y_links ≈ (1−p)^N","explanation":"N is the number of required independent connections and p failure probability per connection.","assumptions":"Illustrative independence model for a defined population. Shared alignment and substrate failures create correlation; redundancy changes the result."}],"prerequisites":["flip-chip-abf-substrate","cowos-s-silicon-interposer"],"learningObjective":"Explain localized bridge geometry and preserve EMIB/EMIB-T boundaries.","workstream":"W05","visualFamily":"package-route","engineeringExample":"Synthetic sensitivity: 10,000 independent required connections at p = 10⁻⁵ give about 90.5% all-good probability. That toy result explains sensitivity to many joints, not Intel’s measured assembly yield.","evidenceNotes":"The Intel brief includes forecasts and manufacturer comparisons. No EMIB-specific queue, utilization or field failure rate is established.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}