{"id":"die-link-compatibility","level":"infrastructure","name":"Die-to-die links and UCIe compatibility","shortName":"Die-to-die links and UCIe compatibility","role":"Defines what adjacent chiplets must agree on to exchange useful data.","description":"A package link connects separately manufactured logic regions through short wires and interfaces. A common standard can define electrical behavior, link training and supported protocols, but compatibility still depends on the selected package class, widths, rates and implementation options. UCIe’s public explanation describes negotiation of operating parameters during initialization. The physical link must also fit the package routing and power budget. A label saying UCIe therefore identifies a framework for interoperability rather than proving that any two purchased chiplets can be assembled together without additional design and qualification work.","specs":[{"label":"Compatibility levels","value":"Physical, link and protocol","context":"Agreement is required at every implemented layer."},{"label":"Bandwidth density","value":"Bytes/s per edge length","context":"Specify the direction and usable interface edge in a comparison."}],"interfaces":[{"name":"Chiplet transmitter","direction":"in","signal":"Encoded data and link-control information"},{"name":"Chiplet receiver","direction":"out","signal":"Validated data delivered to the supported protocol"}],"tradeoff":"Standardized interfaces improve reuse but reserve area, power and routing that a highly specialized link may optimize differently.","whyAI":"Chiplet-based accelerators depend on reliable data exchange before their separate arithmetic and memory resources form a useful device.","related":["package-substrate","interposer","interface-signal-eye"],"sources":[{"title":"Introduction to UCIe webinar: Q&A recap","url":"https://www.uciexpress.org/post/introduction-to-ucie-webinar-q-a-recap"}],"scale":"Micrometers of package wiring to board-scale links; schematic","kind":"architecture","branch":"Chip-to-hall integration","subbranch":"Interface compatibility and electrical budgets","mechanism":["Choose compatible package and electrical options before committing bump locations.","Match protocol support and the meaning of data, control and error responses.","Train the link and negotiate the supported operating parameters.","Verify routing losses, timing and supply noise over intended conditions.","Qualify the integrated package rather than inferring compatibility from individual component labels."],"misconception":"A shared interface name is necessary evidence of a common framework, not sufficient proof of a qualified product combination.","check":{"question":"What must match beyond a connector or standard name?","options":["Physical options and supported protocol behavior","Only the marketing color","Only the total transistor count"],"answer":0,"explanation":"Electrical and logical compatibility must coexist with package routing and operating margins."},"science":[{"title":"Usable link rate","equation":"Buseful = Nlane r η / 8","explanation":"Nlane is lane count, r effective bits/s per lane and η payload efficiency; Buseful is bytes/s in the stated direction.","assumptions":"No lane double-counting; bidirectional aggregate rates require a separate label."}],"prerequisites":["interposer","package-substrate"],"learningObjective":"Separate die-link standardization from implementation compatibility and qualification.","workstream":"W09","visualFamily":"signal-power","engineeringExample":"Synthetic interface: 16 lanes at 8 Gbit/s with 80% payload efficiency yield 12.8 GB/s one way. Summing the reverse direction would describe a different aggregate metric.","evidenceNotes":"The example does not claim a UCIe configuration. Public initialization guidance supplies the mechanism; vendor interoperability test results remain configuration-specific.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}