{"id":"crg-chip-design-realization","level":"system","name":"From architecture contract to a chip","shortName":"Chip design realization","role":"Traverses specification, RTL, verification, synthesis, physical design, tapeout and wafer test.","description":"A chip design is a sequence of constrained transformations. The architecture contract becomes microarchitecture and RTL, then a verified netlist, a placed-and-routed layout, mask data and a process-specific tapeout. The PDK supplies rules and models; timing, power, signal integrity, design-for-test and manufacturability gates prevent an attractive logical design from becoming an untestable or unbuildable die. The CRG makes communication explicit at every handoff: module interfaces, clock and power domains, floorplan distances, package bumps and external links all carry obligations that must survive the transformation.","specs":[{"label":"Design chain","value":"Spec → microarchitecture → RTL → netlist → layout → tapeout","context":"A representative flow; organizations partition responsibilities differently."},{"label":"Closure gates","value":"Functional, timing, power, DFT, physical and manufacturability","context":"Passing one gate does not imply the others pass."}],"interfaces":[{"name":"Architecture contract","direction":"in","signal":"Behavior, interfaces, budgets and verification targets"},{"name":"Tapeout package","direction":"out","signal":"Mask data, signoff evidence and test structures"}],"tradeoff":"More margin and redundancy can improve yield or reliability while consuming area, power, schedule and mask complexity.","whyAI":"The models and kernels that drive AI systems become useful only when their numerical and communication assumptions are realized in a qualified chip and package.","related":["crg-architecture-contract","standard-cell","interconnect","fab-metrology-process-window","known-good-die-test"],"sources":[{"title":"Semi AI Foundry — Communication Theory of Computation Realization","url":"https://semiaifoundry.com/updates/communication-theory-of-computation-realization/"},{"title":"imec — CMOS scaling and system co-optimization","url":"https://www.imec-int.com/en/expertise/cmos-advanced/compute/cmos-scaling"}],"scale":"RTL → layout → masks → wafer test","kind":"process","mechanism":["Refine the architecture contract into clocked state, interfaces and microarchitectural resources.","Verify behavior and synthesize the design using process-specific libraries and models.","Place, route and close timing, power, signal integrity, DFT and physical rules.","Generate masks and send a reviewed tapeout to the chosen foundry process.","Probe, bin and feed measured results back into the design and architecture loop."],"misconception":"Tapeout is not physical realization; wafer yield, test coverage, packaging and system qualification remain.","check":{"question":"Why does a PDK matter in chip design?","options":["It replaces functional verification","It connects design rules and models to a particular manufacturing process","It guarantees every die will pass final test"],"answer":1,"explanation":"A PDK ties the design abstractions to process constraints, but yield and qualification still require measurement."},"science":[{"title":"Timing closure boundary","equation":"T_{clock} \\geq t_{CQ}+t_{logic}+t_{setup}+t_{uncertainty}","explanation":"The clock period must cover launch delay, combinational logic, setup time and an uncertainty budget at the declared path boundary.","assumptions":"A simplified single-clock path; skew, variation, multi-cycle paths and asynchronous crossings need explicit treatment."}],"history":[],"prerequisites":["crg-architecture-contract","standard-cell","interconnect"],"learningObjective":"Name the design transformations and closure gates between an architecture contract and a tested die.","workstream":"CRG","visualFamily":"design-flow","engineeringExample":"A 1 GHz target gives a 1 ns period. If clock-to-Q, logic, setup and uncertainty sum to 1.08 ns, the design fails the declared boundary even if its functional simulation is correct.","evidenceNotes":"The sequence is a representative educational flow. Foundry-specific PDK content and proprietary signoff data are not disclosed.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}