{"id":"crg-architecture-contract","level":"system","name":"Architecture is a contract between computation and silicon","shortName":"Architecture contract","role":"Chooses execution, memory and communication structures that can satisfy a workload contract.","description":"Architecture turns a computation graph into a repeatable organization of execution units, storage levels, interconnects and control. A CPU, GPU, TPU, FPGA, NPU or wafer-scale array realizes similar mathematical operations through different communication patterns and scheduling rules. The CRG view asks which state is retained, where it moves, who controls it, and what happens when a path is full or a unit fails. Architecture is therefore a contract: software assumes a set of behaviors, while implementation must satisfy those behaviors within power, area, timing, test and manufacturing limits.","specs":[{"label":"Contract axes","value":"Execution, storage, communication, control, recovery","context":"A comparison must use the same workload and boundary."},{"label":"Unknowns","value":"Undisclosed internal structures remain unknown","context":"Public architecture claims are not reverse-engineered geometry."}],"interfaces":[{"name":"Workload graph","direction":"in","signal":"Operators, shapes, precision and dependencies"},{"name":"Implementation plan","direction":"out","signal":"Units, memory hierarchy, links, schedules and budgets"}],"tradeoff":"More specialization can improve efficiency for a stable graph while reducing flexibility and increasing software or qualification effort.","whyAI":"The architecture determines whether model-scale tensor traffic becomes useful work or a queue of waiting memory and communication requests.","related":["crg-communication-graph","streaming-multiprocessor","tensor-core","host-cpu","compiler"],"sources":[{"title":"OpenXLA — GPU architecture","url":"https://openxla.org/xla/gpu_architecture"},{"title":"Google Cloud TPU architecture","url":"https://cloud.google.com/tpu/docs/system-architecture"}],"scale":"Graph, architecture, tile and memory hierarchy","kind":"architecture","mechanism":["Extract operator shapes, precision, reuse and synchronization from the workload.","Choose an execution model and dataflow that expose useful parallelism.","Allocate registers, local storage, shared memory and external memory roles.","Specify communication, ordering, fault and recovery behaviors.","Pass the contract to the compiler, RTL and physical-design teams."],"misconception":"An architecture label does not determine workload performance without a compiler path, memory behavior, topology and operating boundary.","check":{"question":"What does the architecture contract connect?","options":["Only the transistor count and logo","The workload’s required state transitions with execution, storage and communication behavior","Only a benchmark score"],"answer":1,"explanation":"Architecture defines how the computation can be carried by a machine under its physical and software constraints."},"science":[{"title":"Workload-bound rate","equation":"R \\leq \\min\\!\\left(P_{compute},\\;B_{memory}I,\\;B_{network}I_{net}\\right)","explanation":"A simple bound compares arithmetic capacity with memory and network delivery capacity after expressing each as a compatible workload rate.","assumptions":"Peak terms, arithmetic intensity and network intensity share a precision, batch and time boundary."}],"history":[],"prerequisites":["crg-communication-graph","streaming-multiprocessor"],"learningObjective":"Compare two architectures by execution model, memory path and communication behavior rather than by a single peak number.","workstream":"CRG","visualFamily":"architecture-array","engineeringExample":"A tensor kernel with low arithmetic intensity may remain memory-bound on a larger accelerator. Changing tile reuse or placing data closer to the unit can raise useful rate without changing the mathematical graph.","evidenceNotes":"The bound is a roofline-style teaching model. Public architecture documentation supplies examples, not a universal product ranking.","labId":"library","scope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.","investigationId":"manufacturing","labScope":"Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism."}